Commit 09888e97 authored by Miquel Raynal's avatar Miquel Raynal
Browse files

Merge tag 'nand/for-6.9' into mtd/next

Raw NAND

The main series brought is an update of the Broadcom support to support
all BCMBCA SoCs and their specificity (ECC, write protection,
configuration straps), plus a few misc fixes and changes in the main
driver. Device tree updates are also part of this PR, initially because
of a misunderstanding on my side.

The STM32_FMC2 controller driver is also upgraded to properly support
MP1 and MP25 SoCs.

A new compatible is added for an Atmel flavor.

Among all these feature changes, there is as well a load of continuous
read related fixes, avoiding more corner conditions and clarifying the
logic. Finally a few miscellaneous fixes are made to the core, the
lpx32xx_mlc, fsl_lbc, Meson and Atmel controller driver, as well as
final one in the Hynix vendor driver.

SPI-NAND

The ESMT support has been extended to match 5 bytes ID to avoid
collisions. Winbond support on its side receives support for W25N04KV
chips.
parents 2842dc9b 4120aa0e
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+1 −0
Original line number Diff line number Diff line
@@ -56,6 +56,7 @@ Required properties:
	"atmel,sama5d4-pmecc"
	"atmel,sama5d2-pmecc"
	"microchip,sam9x60-pmecc"
	"microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc"
- reg: should contain 2 register ranges. The first one is pointing to the PMECC
       block, and the second one to the PMECC_ERRLOC block.

+39 −5
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ title: Broadcom STB NAND Controller
maintainers:
  - Brian Norris <computersforpeace@gmail.com>
  - Kamal Dasu <kdasu.kdev@gmail.com>
  - William Zhang <william.zhang@broadcom.com>

description: |
  The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
@@ -18,9 +19,10 @@ description: |
  supports basic PROGRAM and READ functions, among other features.

  This controller was originally designed for STB SoCs (BCM7xxx) but is now
  available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and
  iProc/Cygnus. Its history includes several similar (but not fully register
  compatible) versions.
  available on a variety of Broadcom SoCs, including some BCM3xxx, MIPS based
  Broadband SoC (BCM63xx), ARM based Broadband SoC (BCMBCA) and iProc/Cygnus.
  Its history includes several similar (but not fully register compatible)
  versions.

  -- Additional SoC-specific NAND controller properties --

@@ -53,7 +55,7 @@ properties:
              - brcm,brcmnand-v7.2
              - brcm,brcmnand-v7.3
          - const: brcm,brcmnand
      - description: BCM63138 SoC-specific NAND controller
      - description: BCMBCA SoC-specific NAND controller
        items:
          - const: brcm,nand-bcm63138
          - enum:
@@ -111,6 +113,13 @@ properties:
      earlier versions of this core that include WP
    type: boolean

  brcm,wp-not-connected:
    description:
      Use this property when WP pin is not physically wired to the NAND chip.
      Write protection feature cannot be used. By default, controller assumes
      the pin is connected and feature is used.
    $ref: /schemas/types.yaml#/definitions/flag

patternProperties:
  "^nand@[a-f0-9]$":
    type: object
@@ -137,6 +146,15 @@ patternProperties:
          layout.
        $ref: /schemas/types.yaml#/definitions/uint32

      brcm,nand-ecc-use-strap:
        description:
          This property requires the host system to get the ECC related
          settings from the SoC NAND boot strap configuration instead of
          the generic NAND ECC settings. This is a common hardware design
          on BCMBCA based boards. This strap ECC option and generic NAND
          ECC option can not be specified at the same time.
        $ref: /schemas/types.yaml#/definitions/flag

    unevaluatedProperties: false

allOf:
@@ -177,6 +195,8 @@ allOf:
            - const: iproc-idm
            - const: iproc-ext
  - if:
      required:
        - interrupts
      properties:
        interrupts:
          minItems: 2
@@ -184,12 +204,26 @@ allOf:
      required:
        - interrupt-names

  - if:
      patternProperties:
        "^nand@[a-f0-9]$":
          required:
            - brcm,nand-ecc-use-strap
    then:
      patternProperties:
        "^nand@[a-f0-9]$":
          properties:
            nand-ecc-strength: false
            nand-ecc-step-size: false
            nand-ecc-maximize: false
            nand-ecc-algo: false
            brcm,nand-oob-sector-size: false

unevaluatedProperties: false

required:
  - reg
  - reg-names
  - interrupts

examples:
  - |
+24 −1
Original line number Diff line number Diff line
@@ -14,10 +14,11 @@ properties:
    enum:
      - st,stm32mp15-fmc2
      - st,stm32mp1-fmc2-nfc
      - st,stm32mp25-fmc2-nfc

  reg:
    minItems: 6
    maxItems: 7
    maxItems: 12

  interrupts:
    maxItems: 1
@@ -92,6 +93,28 @@ allOf:
            - description: Chip select 1 command
            - description: Chip select 1 address space

  - if:
      properties:
        compatible:
          contains:
            const: st,stm32mp25-fmc2-nfc
    then:
      properties:
        reg:
          items:
            - description: Chip select 0 data
            - description: Chip select 0 command
            - description: Chip select 0 address space
            - description: Chip select 1 data
            - description: Chip select 1 command
            - description: Chip select 1 address space
            - description: Chip select 2 data
            - description: Chip select 2 command
            - description: Chip select 2 address space
            - description: Chip select 3 data
            - description: Chip select 3 command
            - description: Chip select 3 address space

required:
  - compatible
  - reg
+14 −0
Original line number Diff line number Diff line
@@ -138,6 +138,20 @@ hsspi: spi@1000 {
			status = "disabled";
		};

		nand_controller: nand-controller@1800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
			reg = <0x1800 0x600>, <0x2000 0x10>;
			reg-names = "nand", "nand-int-base";
			status = "disabled";

			nandcs: nand@0 {
				compatible = "brcm,nandcs";
				reg = <0>;
			};
		};

		uart0: serial@12000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x12000 0x1000>;
+6 −1
Original line number Diff line number Diff line
@@ -229,7 +229,12 @@ nand_controller: nand-controller@2000 {
			reg-names = "nand", "nand-int-base";
			status = "disabled";
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "nand";
			interrupt-names = "nand_ctlrdy";

			nandcs: nand@0 {
				compatible = "brcm,nandcs";
				reg = <0>;
			};
		};

		serial@4400 {
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