Loading arch/powerpc/kernel/iommu.c +0 −10 Original line number Diff line number Diff line Loading @@ -89,7 +89,6 @@ static unsigned long iommu_range_alloc(struct iommu_table *tbl, unsigned int align_order) { unsigned long n, end, i, start; unsigned long start_addr, end_addr; unsigned long limit; int largealloc = npages > 15; int pass = 0; Loading Loading @@ -160,15 +159,6 @@ static unsigned long iommu_range_alloc(struct iommu_table *tbl, } } /* DMA cannot cross 4 GB boundary */ start_addr = (n + tbl->it_offset) << PAGE_SHIFT; end_addr = (end + tbl->it_offset) << PAGE_SHIFT; if ((start_addr >> 32) != (end_addr >> 32)) { end_addr &= 0xffffffff00000000l; start = (end_addr >> PAGE_SHIFT) - tbl->it_offset; goto again; } for (i = n; i < end; i++) if (test_bit(i, tbl->it_map)) { start = i+1; Loading Loading
arch/powerpc/kernel/iommu.c +0 −10 Original line number Diff line number Diff line Loading @@ -89,7 +89,6 @@ static unsigned long iommu_range_alloc(struct iommu_table *tbl, unsigned int align_order) { unsigned long n, end, i, start; unsigned long start_addr, end_addr; unsigned long limit; int largealloc = npages > 15; int pass = 0; Loading Loading @@ -160,15 +159,6 @@ static unsigned long iommu_range_alloc(struct iommu_table *tbl, } } /* DMA cannot cross 4 GB boundary */ start_addr = (n + tbl->it_offset) << PAGE_SHIFT; end_addr = (end + tbl->it_offset) << PAGE_SHIFT; if ((start_addr >> 32) != (end_addr >> 32)) { end_addr &= 0xffffffff00000000l; start = (end_addr >> PAGE_SHIFT) - tbl->it_offset; goto again; } for (i = n; i < end; i++) if (test_bit(i, tbl->it_map)) { start = i+1; Loading