Commit 09e6b306 authored by James Morse's avatar James Morse Committed by Oliver Upton
Browse files

arm64: cpufeature: discover CPU support for MPAM 



ARMv8.4 adds support for 'Memory Partitioning And Monitoring' (MPAM)
which describes an interface to cache and bandwidth controls wherever
they appear in the system.

Add support to detect MPAM. Like SVE, MPAM has an extra id register that
describes some more properties, including the virtualisation support,
which is optional. Detect this separately so we can detect
mismatched/insane systems, but still use MPAM on the host even if the
virtualisation support is missing.

MPAM needs enabling at the highest implemented exception level, otherwise
the register accesses trap. The 'enabled' flag is accessible to lower
exception levels, but its in a register that traps when MPAM isn't enabled.
The cpufeature 'matches' hook is extended to test this on one of the
CPUs, so that firmware can emulate MPAM as disabled if it is reserved
for use by secure world.

Secondary CPUs that appear late could trip cpufeature's 'lower safe'
behaviour after the MPAM properties have been advertised to user-space.
Add a verify call to ensure late secondaries match the existing CPUs.

(If you have a boot failure that bisects here its likely your CPUs
advertise MPAM in the id registers, but firmware failed to either enable
or MPAM, or emulate the trap as if it were disabled)

Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Signed-off-by: default avatarJoey Gouly <joey.gouly@arm.com>
Reviewed-by: default avatarGavin Shan <gshan@redhat.com>
Tested-by: default avatarShameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Reviewed-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20241030160317.2528209-4-joey.gouly@arm.com


Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
parent 23b33d1e

Documentation/arch/arm64/cpu-feature-registers.rst

+2 −0
Original line number Diff line number Diff line
@@ -152,6 +152,8 @@ infrastructure: 
     +------------------------------+---------+---------+

     | DIT                          | [51-48] |    y    |

     +------------------------------+---------+---------+

     | MPAM                         | [43-40] |    n    |

     +------------------------------+---------+---------+

     | SVE                          | [35-32] |    y    |

     +------------------------------+---------+---------+

     | GIC                          | [27-24] |    n    |

arch/arm64/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ struct cpuinfo_arm64 { 
	u64		reg_revidr;

	u64		reg_gmid;

	u64		reg_smidr;

	u64		reg_mpamidr;



	u64		reg_id_aa64dfr0;

	u64		reg_id_aa64dfr1;

arch/arm64/include/asm/cpucaps.h

+5 −0
Original line number Diff line number Diff line
@@ -60,6 +60,11 @@ cpucap_is_possible(const unsigned int cap) 
		return IS_ENABLED(CONFIG_ARM64_WORKAROUND_REPEAT_TLBI);

	case ARM64_WORKAROUND_SPECULATIVE_SSBS:

		return IS_ENABLED(CONFIG_ARM64_ERRATUM_3194386);

	case ARM64_MPAM:

		/*

		 * KVM MPAM support doesn't rely on the host kernel supporting MPAM.

		*/

		return true;

	}



	return true;

arch/arm64/include/asm/cpufeature.h

+17 −0
Original line number Diff line number Diff line
@@ -612,6 +612,13 @@ static inline bool id_aa64pfr1_sme(u64 pfr1) 
	return val > 0;

}



static inline bool id_aa64pfr0_mpam(u64 pfr0)

{

	u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_MPAM_SHIFT);



	return val > 0;

}



static inline bool id_aa64pfr1_mte(u64 pfr1)

{

	u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_EL1_MTE_SHIFT);
@@ -838,6 +845,16 @@ static inline bool system_supports_poe(void) 
		alternative_has_cap_unlikely(ARM64_HAS_S1POE);

}



static inline bool system_supports_mpam(void)

{

	return alternative_has_cap_unlikely(ARM64_MPAM);

}



static __always_inline bool system_supports_mpam_hcr(void)

{

	return alternative_has_cap_unlikely(ARM64_MPAM_HCR);

}



int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt);

bool try_emulate_mrs(struct pt_regs *regs, u32 isn);

arch/arm64/kernel/cpufeature.c

+96 −0
Original line number Diff line number Diff line
@@ -684,6 +684,14 @@ static const struct arm64_ftr_bits ftr_id_dfr1[] = { 
	ARM64_FTR_END,

};



static const struct arm64_ftr_bits ftr_mpamidr[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PMG_MAX_SHIFT, MPAMIDR_EL1_PMG_MAX_WIDTH, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_VPMR_MAX_SHIFT, MPAMIDR_EL1_VPMR_MAX_WIDTH, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_HAS_HCR_SHIFT, 1, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PARTID_MAX_SHIFT, MPAMIDR_EL1_PARTID_MAX_WIDTH, 0),

	ARM64_FTR_END,

};



/*

 * Common ftr bits for a 32bit register with all hidden, strict

 * attributes, with 4bit feature fields and a default safe value of
@@ -804,6 +812,9 @@ static const struct __ftr_reg_entry { 
	ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3),

	ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4),



	/* Op1 = 0, CRn = 10, CRm = 4 */

	ARM64_FTR_REG(SYS_MPAMIDR_EL1, ftr_mpamidr),



	/* Op1 = 1, CRn = 0, CRm = 0 */

	ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
@@ -1163,6 +1174,9 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) 
		cpacr_restore(cpacr);

	}



	if (id_aa64pfr0_mpam(info->reg_id_aa64pfr0))

		init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr);



	if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))

		init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);

}
@@ -1419,6 +1433,11 @@ void update_cpu_features(int cpu, 
		cpacr_restore(cpacr);

	}



	if (id_aa64pfr0_mpam(info->reg_id_aa64pfr0)) {

		taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu,

					info->reg_mpamidr, boot->reg_mpamidr);

	}



	/*

	 * The kernel uses the LDGM/STGM instructions and the number of tags

	 * they read/write depends on the GMID_EL1.BS field. Check that the
@@ -2377,6 +2396,36 @@ cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 
	return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);

}



static bool

test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope)

{

	if (!has_cpuid_feature(entry, scope))

		return false;



	/* Check firmware actually enabled MPAM on this cpu. */

	return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN);

}



static void

cpu_enable_mpam(const struct arm64_cpu_capabilities *entry)

{

	/*

	 * Access by the kernel (at EL1) should use the reserved PARTID

	 * which is configured unrestricted. This avoids priority-inversion

	 * where latency sensitive tasks have to wait for a task that has

	 * been throttled to release the lock.

	 */

	write_sysreg_s(0, SYS_MPAM1_EL1);

}



static bool

test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope)

{

	u64 idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1);



	return idr & MPAMIDR_EL1_HAS_HCR;

}



static const struct arm64_cpu_capabilities arm64_features[] = {

	{

		.capability = ARM64_ALWAYS_BOOT,
@@ -2873,6 +2922,20 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
#endif

	},

#endif

	{

		.desc = "Memory Partitioning And Monitoring",

		.type = ARM64_CPUCAP_SYSTEM_FEATURE,

		.capability = ARM64_MPAM,

		.matches = test_has_mpam,

		.cpu_enable = cpu_enable_mpam,

		ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, MPAM, 1)

	},

	{

		.desc = "Memory Partitioning And Monitoring Virtualisation",

		.type = ARM64_CPUCAP_SYSTEM_FEATURE,

		.capability = ARM64_MPAM_HCR,

		.matches = test_has_mpam_hcr,

	},

	{

		.desc = "NV1",

		.capability = ARM64_HAS_HCR_NV1,
@@ -3396,6 +3459,36 @@ static void verify_hyp_capabilities(void) 
	}

}



static void verify_mpam_capabilities(void)

{

	u64 cpu_idr = read_cpuid(ID_AA64PFR0_EL1);

	u64 sys_idr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);

	u16 cpu_partid_max, cpu_pmg_max, sys_partid_max, sys_pmg_max;



	if (FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, cpu_idr) !=

	    FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, sys_idr)) {

		pr_crit("CPU%d: MPAM version mismatch\n", smp_processor_id());

		cpu_die_early();

	}



	cpu_idr = read_cpuid(MPAMIDR_EL1);

	sys_idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1);

	if (FIELD_GET(MPAMIDR_EL1_HAS_HCR, cpu_idr) !=

	    FIELD_GET(MPAMIDR_EL1_HAS_HCR, sys_idr)) {

		pr_crit("CPU%d: Missing MPAM HCR\n", smp_processor_id());

		cpu_die_early();

	}



	cpu_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, cpu_idr);

	cpu_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, cpu_idr);

	sys_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, sys_idr);

	sys_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, sys_idr);

	if (cpu_partid_max < sys_partid_max || cpu_pmg_max < sys_pmg_max) {

		pr_crit("CPU%d: MPAM PARTID/PMG max values are mismatched\n", smp_processor_id());

		cpu_die_early();

	}

}



/*

 * Run through the enabled system capabilities and enable() it on this CPU.

 * The capabilities were decided based on the available CPUs at the boot time.
@@ -3422,6 +3515,9 @@ static void verify_local_cpu_capabilities(void) 


	if (is_hyp_mode_available())

		verify_hyp_capabilities();



	if (system_supports_mpam())

		verify_mpam_capabilities();

}



void check_local_cpu_capabilities(void)