Commit 0a099232 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/snps: pass encoder to intel_snps_phy_update_psr_power_state() 



Pass encoder to intel_snps_phy_update_psr_power_state(). The encoder
will be more helpful than just port in the subsequent changes.

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/4711919a9834cf4a49fd665009ba9d44b4b42bc4.1710949619.git.jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 684a37a6

drivers/gpu/drm/i915/display/intel_psr.c

+2 −5
Original line number Diff line number Diff line
@@ -1724,7 +1724,6 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, 
{

	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);

	u32 val;



	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
@@ -1752,7 +1751,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, 
		drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",

			    intel_dp->psr.psr2_enabled ? "2" : "1");



	intel_snps_phy_update_psr_power_state(dev_priv, phy, true);

	intel_snps_phy_update_psr_power_state(&dig_port->base, true);

	intel_psr_enable_sink(intel_dp);

	intel_psr_enable_source(intel_dp, crtc_state);

	intel_dp->psr.enabled = true;
@@ -1823,8 +1822,6 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) 
{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

	enum phy phy = intel_port_to_phy(dev_priv,

					 dp_to_dig_port(intel_dp)->base.port);



	lockdep_assert_held(&intel_dp->psr.lock);
@@ -1859,7 +1856,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) 
				     CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0);

	}



	intel_snps_phy_update_psr_power_state(dev_priv, phy, false);

	intel_snps_phy_update_psr_power_state(&dp_to_dig_port(intel_dp)->base, false);



	/* Disable PSR on Sink */

	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);

drivers/gpu/drm/i915/display/intel_snps_phy.c

+4 −2
Original line number Diff line number Diff line
@@ -44,9 +44,11 @@ void intel_snps_phy_wait_for_calibration(struct drm_i915_private *i915) 
	}

}



void intel_snps_phy_update_psr_power_state(struct drm_i915_private *i915,

					   enum phy phy, bool enable)

void intel_snps_phy_update_psr_power_state(struct intel_encoder *encoder,

					   bool enable)

{

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	enum phy phy = intel_port_to_phy(i915, encoder->port);

	u32 val;



	if (!intel_phy_is_snps(i915, phy))

drivers/gpu/drm/i915/display/intel_snps_phy.h

+2 −2
Original line number Diff line number Diff line
@@ -17,8 +17,8 @@ struct intel_mpllb_state; 
enum phy;



void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv);

void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv,

					   enum phy phy, bool enable);

void intel_snps_phy_update_psr_power_state(struct intel_encoder *encoder,

					   bool enable);



int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,

			   struct intel_encoder *encoder);