Commit 0a556150 authored by Kan Liang's avatar Kan Liang Committed by Peter Zijlstra
Browse files

perf/x86/intel: Clean up PEBS-via-PT on hybrid 



The PEBS-via-PT feature is exposed for the e-core of some hybrid
platforms, e.g., ADL and MTL. But it never works.

$ dmesg | grep PEBS
[    1.793888] core: cpu_atom PMU driver: PEBS-via-PT

$ perf record -c 1000 -e '{intel_pt/branch=0/,
cpu_atom/cpu-cycles,aux-output/pp}' -C8
Error:
The sys_perf_event_open() syscall returned with 22 (Invalid argument)
for event (cpu_atom/cpu-cycles,aux-output/pp).
"dmesg | grep -i perf" may provide additional information.

The "PEBS-via-PT" is printed if the corresponding bit of per-PMU
capabilities is set. Since the feature is supported by the e-core HW,
perf sets the bit for e-core. However, for Intel PT, if a feature is not
supported on all CPUs, it is not supported at all. The PEBS-via-PT event
cannot be created successfully.

The PEBS-via-PT is no longer enumerated on the latest hybrid platform. It
will be deprecated on future platforms with Arch PEBS. Let's remove it
from the existing hybrid platforms.

Fixes: d9977c43 ("perf/x86: Register hybrid PMUs")
Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20250129154820.3755948-2-kan.liang@linux.intel.com
parent 469c76a8

arch/x86/events/intel/core.c

+0 −10
Original line number Diff line number Diff line
@@ -4941,11 +4941,6 @@ static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu) 
	else

		pmu->intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS);



	if (pmu->intel_cap.pebs_output_pt_available)

		pmu->pmu.capabilities |= PERF_PMU_CAP_AUX_OUTPUT;

	else

		pmu->pmu.capabilities &= ~PERF_PMU_CAP_AUX_OUTPUT;



	intel_pmu_check_event_constraints(pmu->event_constraints,

					  pmu->cntr_mask64,

					  pmu->fixed_cntr_mask64,
@@ -5023,9 +5018,6 @@ static bool init_hybrid_pmu(int cpu) 


	pr_info("%s PMU driver: ", pmu->name);



	if (pmu->intel_cap.pebs_output_pt_available)

		pr_cont("PEBS-via-PT ");



	pr_cont("\n");



	x86_pmu_show_pmu_cap(&pmu->pmu);
@@ -6370,11 +6362,9 @@ static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus) 
		pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;

		if (pmu->pmu_type & hybrid_small_tiny) {

			pmu->intel_cap.perf_metrics = 0;

			pmu->intel_cap.pebs_output_pt_available = 1;

			pmu->mid_ack = true;

		} else if (pmu->pmu_type & hybrid_big) {

			pmu->intel_cap.perf_metrics = 1;

			pmu->intel_cap.pebs_output_pt_available = 0;

			pmu->late_ack = true;

		}

	}

arch/x86/events/intel/ds.c

+9 −1
Original line number Diff line number Diff line
@@ -2578,7 +2578,15 @@ void __init intel_ds_init(void) 
			}

			pr_cont("PEBS fmt4%c%s, ", pebs_type, pebs_qual);



			if (!is_hybrid() && x86_pmu.intel_cap.pebs_output_pt_available) {

			/*

			 * The PEBS-via-PT is not supported on hybrid platforms,

			 * because not all CPUs of a hybrid machine support it.

			 * The global x86_pmu.intel_cap, which only contains the

			 * common capabilities, is used to check the availability

			 * of the feature. The per-PMU pebs_output_pt_available

			 * in a hybrid machine should be ignored.

			 */

			if (x86_pmu.intel_cap.pebs_output_pt_available) {

				pr_cont("PEBS-via-PT, ");

				x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_AUX_OUTPUT;

			}