Commit 0a5c060b authored by Tim Huang's avatar Tim Huang Committed by Alex Deucher
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drm/amdgpu: fix incorrect MALL size for GFX1151 



On GFX1151, the reported MALL cache size reflects only
half of its actual size; this adjustment corrects the discrepancy.

Signed-off-by: default avatarTim Huang <tim.huang@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarYifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4367ee3e

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

+12 −0
Original line number Diff line number Diff line
@@ -748,6 +748,18 @@ static int gmc_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 
	adev->gmc.vram_type = vram_type;

	adev->gmc.vram_vendor = vram_vendor;



	/* The mall_size is already calculated as mall_size_per_umc * num_umc.

	 * However, for gfx1151, which features a 2-to-1 UMC mapping,

	 * the result must be multiplied by 2 to determine the actual mall size.

	 */

	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {

	case IP_VERSION(11, 5, 1):

		adev->gmc.mall_size *= 2;

		break;

	default:

		break;

	}



	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {

	case IP_VERSION(11, 0, 0):

	case IP_VERSION(11, 0, 1):