Commit 0a62732e authored by Mario Limonciello (AMD)'s avatar Mario Limonciello (AMD) Committed by Alex Deucher
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drm/amd/display: Detect panel type from VSDB



[Why]
The AMD VSDB contains two bits that indicate the type of panel connected.
This can be useful for policy decisions based upon panel technology.

[How]
Read the bits for the panel type when parsing VSDB and store them in
the dc_link.

Reviewed-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarMario Limonciello (AMD) <superm1@kernel.org>
Signed-off-by: default avatarMatthew Stewart <matthew.stewart2@amd.com>
Tested-by: default avatarDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8cee6290
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+15 −0
Original line number Diff line number Diff line
@@ -13146,9 +13146,24 @@ static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,

		if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID &&
				amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) {
			u8 panel_type;
			vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false;
			vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3;
			drm_dbg_kms(aconnector->base.dev, "Panel supports Replay Mode: %d\n", vsdb_info->replay_mode);
			panel_type = (amd_vsdb->color_space_eotf_support & AMD_VDSB_VERSION_3_PANEL_TYPE_MASK) >> AMD_VDSB_VERSION_3_PANEL_TYPE_SHIFT;
			switch (panel_type) {
			case AMD_VSDB_PANEL_TYPE_OLED:
				aconnector->dc_link->panel_type = PANEL_TYPE_OLED;
				break;
			case AMD_VSDB_PANEL_TYPE_MINILED:
				aconnector->dc_link->panel_type = PANEL_TYPE_MINILED;
				break;
			default:
				aconnector->dc_link->panel_type = PANEL_TYPE_NONE;
				break;
			}
			drm_dbg_kms(aconnector->base.dev, "Panel type: %d\n",
				    aconnector->dc_link->panel_type);

			return true;
		}
+11 −0
Original line number Diff line number Diff line
@@ -55,8 +55,17 @@

#define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A
#define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40
#define AMD_VDSB_VERSION_3_PANEL_TYPE_MASK 0xC0
#define AMD_VDSB_VERSION_3_PANEL_TYPE_SHIFT 6
#define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x3

enum amd_vsdb_panel_type {
	AMD_VSDB_PANEL_TYPE_DEFAULT = 0,
	AMD_VSDB_PANEL_TYPE_MINILED,
	AMD_VSDB_PANEL_TYPE_OLED,
	AMD_VSDB_PANEL_TYPE_RESERVED,
};

#define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL)

/*
@@ -92,6 +101,8 @@ struct amd_vsdb_block {
	unsigned char ieee_id[3];
	unsigned char version;
	unsigned char feature_caps;
	unsigned char reserved[3];
	unsigned char color_space_eotf_support;
};

struct common_irq_params {
+1 −0
Original line number Diff line number Diff line
@@ -1734,6 +1734,7 @@ struct dc_scratch_space {
	bool link_powered_externally;	// Used to bypass hardware sequencing delays when panel is powered down forcibly

	struct dc_panel_config panel_config;
	enum dc_panel_type panel_type;
	struct phy_state phy_state;
	uint32_t phy_transition_bitmask;
	// BW ALLOCATON USB4 ONLY
+7 −0
Original line number Diff line number Diff line
@@ -964,6 +964,13 @@ struct display_endpoint_id {
	enum display_endpoint_type ep_type;
};

enum dc_panel_type {
	PANEL_TYPE_NONE = 0, // UNKONWN, not determined yet
	PANEL_TYPE_LCD = 1,
	PANEL_TYPE_OLED = 2,
	PANEL_TYPE_MINILED = 3,
};

enum backlight_control_type {
	BACKLIGHT_CONTROL_PWM = 0,
	BACKLIGHT_CONTROL_VESA_AUX = 1,