Commit 0a9615d5 authored by Daniel Golle's avatar Daniel Golle Committed by Matthias Brugger
Browse files

arm64: dts: mt7986: add thermal and efuse

parent a4366b56
Loading
Loading
Loading
Loading
+35 −1
Original line number Diff line number Diff line
@@ -337,6 +337,15 @@ spi1: spi@1100b000 {
			status = "disabled";
		};

		auxadc: adc@1100d000 {
			compatible = "mediatek,mt7986-auxadc";
			reg = <0 0x1100d000 0 0x1000>;
			clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
			clock-names = "main";
			#io-channel-cells = <1>;
			status = "disabled";
		};

		ssusb: usb@11200000 {
			compatible = "mediatek,mt7986-xhci",
				     "mediatek,mtk-xhci";
@@ -375,6 +384,21 @@ mmc0: mmc@11230000 {
			status = "disabled";
		};

		thermal: thermal@1100c800 {
			#thermal-sensor-cells = <1>;
			compatible = "mediatek,mt7986-thermal";
			reg = <0 0x1100c800 0 0x800>;
			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&infracfg CLK_INFRA_THERM_CK>,
				 <&infracfg CLK_INFRA_ADC_26M_CK>,
				 <&infracfg CLK_INFRA_ADC_FRC_CK>;
			clock-names = "therm", "auxadc", "adc_32k";
			mediatek,auxadc = <&auxadc>;
			mediatek,apmixedsys = <&apmixedsys>;
			nvmem-cells = <&thermal_calibration>;
			nvmem-cell-names = "calibration-data";
		};

		pcie: pcie@11280000 {
			compatible = "mediatek,mt7986-pcie",
				     "mediatek,mt8192-pcie";
@@ -426,6 +450,17 @@ pcie_port: pcie-phy@11c00000 {
			};
		};

		efuse: efuse@11d00000 {
			compatible = "mediatek,mt7986-efuse", "mediatek,efuse";
			reg = <0 0x11d00000 0 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;

			thermal_calibration: calib@274 {
				reg = <0x274 0xc>;
			};
		};

		usb_phy: t-phy@11e10000 {
			compatible = "mediatek,mt7986-tphy",
				     "mediatek,generic-tphy-v2";
@@ -567,5 +602,4 @@ wifi: wifi@18000000 {
			memory-region = <&wmcpu_emi>;
		};
	};

};