Commit 0b042c72 authored by Piyush Malgujar's avatar Piyush Malgujar Committed by Andi Shyti
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i2c: octeon: Add platform prefix to macros 



The macros for TWSI register's offset are generically
named, rename them to be platform specific macros by
adding 'OCTEON_REG' as prefix.

Signed-off-by: default avatarPiyush Malgujar <pmalgujar@marvell.com>
Signed-off-by: default avatarAndi Shyti <andi.shyti@kernel.org>
parent 03240f82

drivers/i2c/busses/i2c-octeon-core.c

+18 −18
Original line number Diff line number Diff line
@@ -85,7 +85,7 @@ static int octeon_i2c_wait(struct octeon_i2c *i2c) 


static bool octeon_i2c_hlc_test_valid(struct octeon_i2c *i2c)

{

	return (__raw_readq(i2c->twsi_base + SW_TWSI(i2c)) & SW_TWSI_V) == 0;

	return (__raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)) & SW_TWSI_V) == 0;

}



static void octeon_i2c_hlc_int_clear(struct octeon_i2c *i2c)
@@ -185,10 +185,10 @@ static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read) 


	/*

	 * This is ugly... in HLC mode the status is not in the status register

	 * but in the lower 8 bits of SW_TWSI.

	 * but in the lower 8 bits of OCTEON_REG_SW_TWSI.

	 */

	if (i2c->hlc_enabled)

		stat = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));

		stat = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));

	else

		stat = octeon_i2c_stat_read(i2c);
@@ -424,12 +424,12 @@ static int octeon_i2c_hlc_read(struct octeon_i2c *i2c, struct i2c_msg *msgs) 
	else

		cmd |= SW_TWSI_OP_7;



	octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));

	octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));

	ret = octeon_i2c_hlc_wait(i2c);

	if (ret)

		goto err;



	cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));

	cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));

	if ((cmd & SW_TWSI_R) == 0)

		return octeon_i2c_check_status(i2c, false);
@@ -437,7 +437,7 @@ static int octeon_i2c_hlc_read(struct octeon_i2c *i2c, struct i2c_msg *msgs) 
		msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;



	if (msgs[0].len > 4) {

		cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c));

		cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));

		for (i = 0; i  < msgs[0].len - 4 && i < 4; i++, j--)

			msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;

	}
@@ -474,15 +474,15 @@ static int octeon_i2c_hlc_write(struct octeon_i2c *i2c, struct i2c_msg *msgs) 


		for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)

			ext |= (u64)msgs[0].buf[j] << (8 * i);

		octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));

		octeon_i2c_writeq_flush(ext, i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));

	}



	octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));

	octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));

	ret = octeon_i2c_hlc_wait(i2c);

	if (ret)

		goto err;



	cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));

	cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));

	if ((cmd & SW_TWSI_R) == 0)

		return octeon_i2c_check_status(i2c, false);
@@ -515,19 +515,19 @@ static int octeon_i2c_hlc_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs 
		cmd |= SW_TWSI_EIA;

		ext = (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;

		cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;

		octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));

		octeon_i2c_writeq_flush(ext, i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));

	} else {

		cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;

	}



	octeon_i2c_hlc_int_clear(i2c);

	octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));

	octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));



	ret = octeon_i2c_hlc_wait(i2c);

	if (ret)

		goto err;



	cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));

	cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));

	if ((cmd & SW_TWSI_R) == 0)

		return octeon_i2c_check_status(i2c, false);
@@ -535,7 +535,7 @@ static int octeon_i2c_hlc_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs 
		msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;



	if (msgs[1].len > 4) {

		cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c));

		cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));

		for (i = 0; i  < msgs[1].len - 4 && i < 4; i++, j--)

			msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;

	}
@@ -582,16 +582,16 @@ static int octeon_i2c_hlc_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msg 
		set_ext = true;

	}

	if (set_ext)

		octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));

		octeon_i2c_writeq_flush(ext, i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));



	octeon_i2c_hlc_int_clear(i2c);

	octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));

	octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));



	ret = octeon_i2c_hlc_wait(i2c);

	if (ret)

		goto err;



	cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));

	cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));

	if ((cmd & SW_TWSI_R) == 0)

		return octeon_i2c_check_status(i2c, false);
@@ -737,13 +737,13 @@ void octeon_i2c_set_clock(struct octeon_i2c *i2c) 
	if (is_plat_otx2) {

		u64 mode;



		mode = __raw_readq(i2c->twsi_base + MODE(i2c));

		mode = __raw_readq(i2c->twsi_base + OCTEON_REG_MODE(i2c));

		/* Set REFCLK_SRC and HS_MODE in TWSX_MODE register */

		if (!IS_LS_FREQ(i2c->twsi_freq))

			mode |= TWSX_MODE_HS_MASK;

		else

			mode &= ~TWSX_MODE_HS_MASK;

		octeon_i2c_writeq_flush(mode, i2c->twsi_base + MODE(i2c));

		octeon_i2c_writeq_flush(mode, i2c->twsi_base + OCTEON_REG_MODE(i2c));

	}

}

drivers/i2c/busses/i2c-octeon-core.h

+13 −13
Original line number Diff line number Diff line
@@ -97,10 +97,10 @@ struct octeon_i2c_reg_offset { 
	unsigned int mode;

};



#define SW_TWSI(x)	(x->roff.sw_twsi)

#define TWSI_INT(x)	(x->roff.twsi_int)

#define SW_TWSI_EXT(x)	(x->roff.sw_twsi_ext)

#define MODE(x)		((x)->roff.mode)

#define OCTEON_REG_SW_TWSI(x)		((x)->roff.sw_twsi)

#define OCTEON_REG_TWSI_INT(x)		((x)->roff.twsi_int)

#define OCTEON_REG_SW_TWSI_EXT(x)	((x)->roff.sw_twsi_ext)

#define OCTEON_REG_MODE(x)		((x)->roff.mode)



/* Set REFCLK_SRC and HS_MODE in TWSX_MODE register */

#define TWSX_MODE_REFCLK_SRC	BIT(4)
@@ -143,16 +143,16 @@ static inline void octeon_i2c_writeq_flush(u64 val, void __iomem *addr) 
 * @eop_reg: Register selector

 * @data: Value to be written

 *

 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.

 * The I2C core registers are accessed indirectly via the OCTEON_REG_SW_TWSI CSR.

 */

static inline void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data)

{

	int tries = 1000;

	u64 tmp;



	__raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI(i2c));

	__raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));

	do {

		tmp = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));

		tmp = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));

		if (--tries < 0)

			return;

	} while ((tmp & SW_TWSI_V) != 0);
@@ -178,9 +178,9 @@ static inline int octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg, 
	int tries = 1000;

	u64 tmp;



	__raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI(i2c));

	__raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));

	do {

		tmp = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));

		tmp = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));

		if (--tries < 0) {

			/* signal that the returned data is invalid */

			if (error)
@@ -200,24 +200,24 @@ static inline int octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg, 
	octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT, NULL)



/**

 * octeon_i2c_read_int - read the TWSI_INT register

 * octeon_i2c_read_int - read the OCTEON_REG_TWSI_INT register

 * @i2c: The struct octeon_i2c

 *

 * Returns the value of the register.

 */

static inline u64 octeon_i2c_read_int(struct octeon_i2c *i2c)

{

	return __raw_readq(i2c->twsi_base + TWSI_INT(i2c));

	return __raw_readq(i2c->twsi_base + OCTEON_REG_TWSI_INT(i2c));

}



/**

 * octeon_i2c_write_int - write the TWSI_INT register

 * octeon_i2c_write_int - write the OCTEON_REG_TWSI_INT register

 * @i2c: The struct octeon_i2c

 * @data: Value to be written

 */

static inline void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)

{

	octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT(i2c));

	octeon_i2c_writeq_flush(data, i2c->twsi_base + OCTEON_REG_TWSI_INT(i2c));

}



#define IS_LS_FREQ(twsi_freq)	((twsi_freq) <= 400000)