Commit 0b29600a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'irq-drivers-2025-07-27' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull interrupt chip driver updates from Thomas Gleixner:

 - Add support of forced affinity setting to yet offline CPUs for the
   MIPS-GIC to ensure that the affinity of per CPU interrupts can be set
   during the early bringup phase of a secondary CPU in the hotplug code
   before the CPU is set online and interrupts are enabled

 - Add support for the MIPS (RISC-V !?!?) P8700 SoC in the ACLINT_SSWI
   interrupt chip

 - Make the interrupt routing to RISV-V harts specification compliant so
   it supports arbitrary hart indices

 - Add a command line parameter and related handling to disable the
   generic RISCV IMSIC mechanism on platforms which use a trap-emulated
   IMSIC. Unfortunatly this is required because there is no mechanism
   available to discover this programatically.

 - Enable wakeup sources on the Renesas RZV2H driver

 - Convert interrupt chip drivers, which use a open coded variant of
   msi_create_parent_irq_domain() to use the new functionality

 - Convert interrupt chip drivers, which use the old style two level
   implementation of MSI support over to the MSI parent mechanism to
   prepare for removing at least one of the three PCI/MSI backend
   variants.

 - The usual cleanups and improvements all over the place

* tag 'irq-drivers-2025-07-27' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (28 commits)
  irqchip/renesas-irqc: Convert to DEFINE_SIMPLE_DEV_PM_OPS()
  irqchip/renesas-intc-irqpin: Convert to DEFINE_SIMPLE_DEV_PM_OPS()
  irqchip/riscv-imsic: Add kernel parameter to disable IPIs
  irqchip/gic-v3: Fix GICD_CTLR register naming
  irqchip/ls-scfg-msi: Fix NULL dereference in error handling
  irqchip/ls-scfg-msi: Switch to use msi_create_parent_irq_domain()
  irqchip/armada-370-xp: Switch to msi_create_parent_irq_domain()
  irqchip/alpine-msi: Switch to msi_create_parent_irq_domain()
  irqchip/alpine-msi: Convert to __free
  irqchip/alpine-msi: Convert to lock guards
  irqchip/alpine-msi: Clean up whitespace style
  irqchip/sg2042-msi: Switch to msi_create_parent_irq_domain()
  irqchip/loongson-pch-msi.c: Switch to msi_create_parent_irq_domain()
  irqchip/imx-mu-msi: Convert to msi_create_parent_irq_domain() helper
  irqchip/riscv-imsic: Convert to msi_create_parent_irq_domain() helper
  irqchip/bcm2712-mip: Switch to msi_create_parent_irq_domain()
  irqdomain: Add device pointer to irq_domain_info and msi_domain_info
  irqchip/renesas-rzv2h: Remove unneeded includes
  irqchip/renesas-rzv2h: Enable SKIP_SET_WAKE and MASK_ON_SUSPEND
  irqchip/aslint-sswi: Resolve hart index
  ...
parents b34111a8 2aad477b

Documentation/admin-guide/kernel-parameters.txt

+7 −0
Original line number Diff line number Diff line
@@ -2538,6 +2538,13 @@ 
			requires the kernel to be built with

			CONFIG_ARM64_PSEUDO_NMI.



	irqchip.riscv_imsic_noipi

			[RISC-V,EARLY]

			Force the kernel to not use IMSIC software injected MSIs

			as IPIs. Intended for system where IMSIC is trap-n-emulated,

			and thus want to reduce MMIO traps when triggering IPIs

			to multiple harts.



	irqfixup	[HW]

			When an interrupt is not handled search all handlers

			for it. Intended to get systems with badly broken

Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml

+55 −9
Original line number Diff line number Diff line
@@ -4,23 +4,32 @@ 
$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: T-HEAD C900 ACLINT Supervisor-level Software Interrupt Device

title: ACLINT Supervisor-level Software Interrupt Device



maintainers:

  - Inochi Amaoto <inochiama@outlook.com>



description:

  The SSWI device is a part of the THEAD ACLINT device. It provides

  supervisor-level IPI functionality for a set of HARTs on a THEAD

  platform. It provides a register to set an IPI (SETSSIP) for each

  HART connected to the SSWI device.

  The SSWI device is a part of the ACLINT device. It provides

  supervisor-level IPI functionality for a set of HARTs on a supported

  platforms. It provides a register to set an IPI (SETSSIP) for each

  HART connected to the SSWI device. See draft specification

  https://github.com/riscvarchive/riscv-aclint



  Following variants of the SSWI ACLINT supported, using dedicated

  compatible string

  - THEAD C900

  - MIPS P8700



properties:

  compatible:

    items:

    oneOf:

      - items:

          - enum:

              - sophgo,sg2044-aclint-sswi

          - const: thead,c900-aclint-sswi

      - items:

          - const: mips,p8700-aclint-sswi



  reg:

    maxItems: 1
@@ -34,6 +43,14 @@ properties: 
    minItems: 1

    maxItems: 4095



  riscv,hart-indexes:

    $ref: /schemas/types.yaml#/definitions/uint32-array

    minItems: 1

    maxItems: 4095

    description:

      A list of hart indexes that APLIC should use to address each hart

      that is mentioned in the "interrupts-extended"



additionalProperties: false



required:
@@ -43,8 +60,22 @@ required: 
  - interrupt-controller

  - interrupts-extended



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: mips,p8700-aclint-sswi

    then:

      required:

        - riscv,hart-indexes

    else:

      properties:

        riscv,hart-indexes: false



examples:

  - |

    //Example 1

    interrupt-controller@94000000 {

      compatible = "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi";

      reg = <0x94000000 0x00004000>;
@@ -55,4 +86,19 @@ examples: 
                            <&cpu3intc 1>,

                            <&cpu4intc 1>;

    };



  - |

    //Example 2

    interrupt-controller@94000000 {

      compatible = "mips,p8700-aclint-sswi";

      reg = <0x94000000 0x00004000>;

      #interrupt-cells = <0>;

      interrupt-controller;

      interrupts-extended = <&cpu1intc 1>,

                            <&cpu2intc 1>,

                            <&cpu3intc 1>,

                            <&cpu4intc 1>;

      riscv,hart-indexes = <0x0 0x1 0x10 0x11>;

    };



...

arch/riscv/include/asm/irq.h

+2 −0
Original line number Diff line number Diff line
@@ -22,6 +22,8 @@ void arch_trigger_cpumask_backtrace(const cpumask_t *mask, int exclude_cpu); 
void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void));



struct fwnode_handle *riscv_get_intc_hwnode(void);

int riscv_get_hart_index(struct fwnode_handle *fwnode, u32 logical_index,

			 u32 *hart_index);



#ifdef CONFIG_ACPI

arch/riscv/kernel/irq.c

+34 −0
Original line number Diff line number Diff line
@@ -32,6 +32,40 @@ struct fwnode_handle *riscv_get_intc_hwnode(void) 
}

EXPORT_SYMBOL_GPL(riscv_get_intc_hwnode);



/**

 * riscv_get_hart_index() - get hart index for interrupt delivery

 * @fwnode: interrupt controller node

 * @logical_index: index within the "interrupts-extended" property

 * @hart_index: filled with the hart index to use

 *

 * RISC-V uses term "hart index" for its interrupt controllers, for the

 * purpose of the interrupt routing to destination harts.

 * It may be arbitrary numbers assigned to each destination hart in context

 * of the particular interrupt domain.

 *

 * These numbers encoded in the optional property "riscv,hart-indexes"

 * that should contain hart index for each interrupt destination in the same

 * order as in the "interrupts-extended" property. If this property

 * not exist, it assumed equal to the logical index, i.e. index within the

 * "interrupts-extended" property.

 *

 * Return: error code

 */

int riscv_get_hart_index(struct fwnode_handle *fwnode, u32 logical_index,

			 u32 *hart_index)

{

	static const char *prop_hart_index = "riscv,hart-indexes";

	struct device_node *np = to_of_node(fwnode);



	if (!np || !of_property_present(np, prop_hart_index)) {

		*hart_index = logical_index;

		return 0;

	}



	return of_property_read_u32_index(np, prop_hart_index,

					  logical_index, hart_index);

}



#ifdef CONFIG_IRQ_STACKS

#include <asm/irq_stack.h>

drivers/irqchip/Kconfig

+14 −4
Original line number Diff line number Diff line
@@ -80,12 +80,14 @@ config ARMADA_370_XP_IRQ 
	bool

	select GENERIC_IRQ_CHIP

	select PCI_MSI if PCI

	select IRQ_MSI_LIB if PCI

	select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP



config ALPINE_MSI

	bool

	depends on PCI

	select PCI_MSI

	select IRQ_MSI_LIB

	select GENERIC_IRQ_CHIP



config AL_FIC
@@ -435,6 +437,7 @@ config LS_SCFG_MSI 
	def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE

	select IRQ_MSI_IOMMU

	depends on PCI_MSI

	select IRQ_MSI_LIB



config PARTITION_PERCPU

	bool
@@ -635,18 +638,25 @@ config STARFIVE_JH8100_INTC 


	  If you don't know what to do here, say Y.



config THEAD_C900_ACLINT_SSWI

	bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller"

config ACLINT_SSWI

	bool "RISC-V ACLINT S-mode IPI Interrupt Controller"

	depends on RISCV

	depends on SMP

	select IRQ_DOMAIN_HIERARCHY

	select GENERIC_IRQ_IPI_MUX

	help

	  This enables support for T-HEAD specific ACLINT SSWI device

	  support.

	  This enables support for variants of the RISC-V ACLINT-SSWI device.

	  Supported variants are:

	  - T-HEAD, with compatible "thead,c900-aclint-sswi"

	  - MIPS P8700, with compatible "mips,p8700-aclint-sswi"



	  If you don't know what to do here, say Y.



# Backwards compatibility so oldconfig does not drop it.

config THEAD_C900_ACLINT_SSWI

	bool

	select ACLINT_SSWI



config EXYNOS_IRQ_COMBINER

	bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST

	depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST