Commit 0b2f7be5 authored by Nitin Gote's avatar Nitin Gote Committed by Lucas De Marchi
Browse files

drm/xe/xe3: Add WA_14024681466 for Xe3_LPG 



Apply WA_14024681466 to Xe3_LPG graphics IP versions from 30.00 to 30.05.

v2: (Matthew Roper)
   - Remove stepping filter as workaround applies to all steppings.
   - Add an engine class filter so it only applies to the RENDER engine.

Signed-off-by: default avatarNitin Gote <nitin.r.gote@intel.com>
Link: https://patch.msgid.link/20251027092643.335904-1-nitin.r.gote@intel.com


Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
(cherry picked from commit 071089a6)
Cc: stable@vger.kernel.org # v6.16+
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent e9a6fb0b

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -168,6 +168,7 @@ 


#define XEHP_SLICE_COMMON_ECO_CHICKEN1		XE_REG_MCR(0x731c, XE_REG_OPTION_MASKED)

#define   MSC_MSAA_REODER_BUF_BYPASS_DISABLE	REG_BIT(14)

#define   FAST_CLEAR_VALIGN_FIX			REG_BIT(13)



#define XE2LPM_CCCHKNREG1			XE_REG(0x82a8)

drivers/gpu/drm/xe/xe_wa.c

+4 −0
Original line number Diff line number Diff line
@@ -916,6 +916,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = { 
	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3003), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))

	},

	{ XE_RTP_NAME("14024681466"),

	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, FAST_CLEAR_VALIGN_FIX))

	},

};



static __maybe_unused const struct xe_rtp_entry oob_was[] = {