Commit 0ba9b155 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-next-2024-07-26' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
 "Fixes for rc1, mostly amdgpu, i915 and xe, with some other misc ones,
  doesn't seem to be anything too serious.

  amdgpu:
   - Bump driver version for GFX12 DCC
   - DC documention warning fixes
   - VCN unified queue power fix
   - SMU fix
   - RAS fix
   - Display corruption fix
   - SDMA 5.2 workaround
   - GFX12 fixes
   - Uninitialized variable fix
   - VCN/JPEG 4.0.3 fixes
   - Misc display fixes
   - RAS fixes
   - VCN4/5 harvest fix
   - GPU reset fix

  i915:
   - Reset intel_dp->link_trained before retraining the link
   - Don't switch the LTTPR mode on an active link
   - Do not consider preemption during execlists_dequeue for gen8
   - Allow NULL memory region

  xe:
   - xe_exec ioctl minor fix on sync entry cleanup upon error
   - SRIOV: limit VF LMEM provisioning
   - Wedge mode fixes

  v3d:
   - fix indirect dispatch on newer v3d revs

  panel:
   - fix panel backlight bindings"

* tag 'drm-next-2024-07-26' of https://gitlab.freedesktop.org/drm/kernel: (39 commits)
  drm/amdgpu: reset vm state machine after gpu reset(vram lost)
  drm/amdgpu: add missed harvest check for VCN IP v4/v5
  drm/amdgpu: Fix eeprom max record count
  drm/amdgpu: fix ras UE error injection failure issue
  drm/amd/display: Remove ASSERT if significance is zero in math_ceil2
  drm/amd/display: Check for NULL pointer
  drm/amdgpu/vcn: Use offsets local to VCN/JPEG in VF
  drm/amdgpu: Add empty HDP flush function to VCN v4.0.3
  drm/amdgpu: Add empty HDP flush function to JPEG v4.0.3
  drm/amd/amdgpu: Fix uninitialized variable warnings
  drm/amdgpu: Fix atomics on GFX12
  drm/amdgpu/sdma5.2: Update wptr registers as well as doorbell
  drm/i915: Allow NULL memory region
  drm/i915/gt: Do not consider preemption during execlists_dequeue for gen8
  dt-bindings: display: panel: samsung,atna33xc20: Document ATNA45AF01
  drm/xe: Don't suspend device upon wedge
  drm/xe: Wedge the entire device
  drm/xe/pf: Limit fair VF LMEM provisioning
  drm/xe/exec: Fix minor bug related to xe_sync_entry_cleanup
  drm/amd/display: fix corruption with high refresh rates on DCN 3.0
  ...
parents 65ad409e d4ef5d2b
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+7 −1
Original line number Diff line number Diff line
@@ -14,7 +14,13 @@ allOf:

properties:
  compatible:
    const: samsung,atna33xc20
    oneOf:
      # Samsung 13.3" FHD (1920x1080 pixels) eDP AMOLED panel
      - const: samsung,atna33xc20
      # Samsung 14.5" WQXGA+ (2880x1800 pixels) eDP AMOLED panel
      - items:
          - const: samsung,atna45af01
          - const: samsung,atna33xc20

  enable-gpios: true
  port: true
+6 −29
Original line number Diff line number Diff line
@@ -8,37 +8,22 @@ and the code documentation when it is automatically generated.
DCHUBBUB
--------

.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
   :doc: overview

.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
   :export:

.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
   :internal:

HUBP
----

.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
   :doc: overview

.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
   :export:

.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
   :internal:

DPP
---

.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
   :doc: overview

.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
   :export:

.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
   :internal:

MPC
@@ -47,11 +32,9 @@ MPC
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
   :doc: overview

.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
   :export:

.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
   :internal:
   :no-identifiers: mpcc_blnd_cfg mpcc_alpha_blend_mode

OPP
---
@@ -59,20 +42,14 @@ OPP
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
   :doc: overview

.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
   :export:

.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
   :internal:

DIO
---

.. kernel-doc:: drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
   :doc: overview

.. kernel-doc:: drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h
   :export:

.. kernel-doc:: drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h
.. kernel-doc:: drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
   :internal:
+2 −2
Original line number Diff line number Diff line
@@ -132,7 +132,7 @@ The DRM blend mode and its elements are then mapped by AMDGPU display manager
(MPC), as follows:

.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
   :functions: mpcc_blnd_cfg
   :identifiers: mpcc_blnd_cfg

Therefore, the blending configuration for a single MPCC instance on the MPC
tree is defined by :c:type:`mpcc_blnd_cfg`, where
@@ -144,7 +144,7 @@ alpha and plane alpha values. It sets one of the three modes for
:c:type:`MPCC_ALPHA_BLND_MODE`, as described below.

.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
   :functions: mpcc_alpha_blend_mode
   :identifiers: mpcc_alpha_blend_mode

DM then maps the elements of `enum mpcc_alpha_blend_mode` to those in the DRM
blend formula, as follows:
+2 −1
Original line number Diff line number Diff line
@@ -106,7 +106,8 @@ amdgpu-y += \
	df_v1_7.o \
	df_v3_6.o \
	df_v4_3.o \
	df_v4_6_2.o
	df_v4_6_2.o \
	df_v4_15.o

# add GMC block
amdgpu-y += \
+1 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ struct amdgpu_df_hash_status {
struct amdgpu_df_funcs {
	void (*sw_init)(struct amdgpu_device *adev);
	void (*sw_fini)(struct amdgpu_device *adev);
	void (*hw_init)(struct amdgpu_device *adev);
	void (*enable_broadcast_mode)(struct amdgpu_device *adev,
				      bool enable);
	u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
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