Commit 0bb5b6fa authored by Lorenzo Pieralisi's avatar Lorenzo Pieralisi Committed by Marc Zyngier
Browse files

arm64: cpucaps: Rename GICv3 CPU interface capability 



In preparation for adding a GICv5 CPU interface capability,
rework the existing GICv3 CPUIF capability - change its name and
description so that the subsequent GICv5 CPUIF capability
can be added with a more consistent naming on top.

Suggested-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: default avatarMarc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-16-12e71f1b3528@kernel.org


Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent 25374470

arch/arm64/kernel/cpufeature.c

+5 −5
Original line number Diff line number Diff line
@@ -2296,11 +2296,11 @@ static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 
				   int scope)

{

	/*

	 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU

	 * ARM64_HAS_GICV3_CPUIF has a lower index, and is a boot CPU

	 * feature, so will be detected earlier.

	 */

	BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS);

	if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS))

	BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GICV3_CPUIF);

	if (!cpus_have_cap(ARM64_HAS_GICV3_CPUIF))

		return false;



	return enable_pseudo_nmi;
@@ -2496,8 +2496,8 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.matches = has_always,

	},

	{

		.desc = "GIC system register CPU interface",

		.capability = ARM64_HAS_GIC_CPUIF_SYSREGS,

		.desc = "GICv3 CPU interface",

		.capability = ARM64_HAS_GICV3_CPUIF,

		.type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,

		.matches = has_useable_gicv3_cpuif,

		ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP)

arch/arm64/tools/cpucaps

+1 −1
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ HAS_GENERIC_AUTH 
HAS_GENERIC_AUTH_ARCH_QARMA3

HAS_GENERIC_AUTH_ARCH_QARMA5

HAS_GENERIC_AUTH_IMP_DEF

HAS_GIC_CPUIF_SYSREGS

HAS_GICV3_CPUIF

HAS_GIC_PRIO_MASKING

HAS_GIC_PRIO_RELAXED_SYNC

HAS_HCR_NV1

drivers/irqchip/irq-gic.c

+1 −1
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ 


static void gic_check_cpu_features(void)

{

	WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_GIC_CPUIF_SYSREGS),

	WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_GICV3_CPUIF),

			TAINT_CPU_OUT_OF_SPEC,

			"GICv3 system registers enabled, broken firmware!\n");

}