Commit 0bc519d2 authored by Lucas De Marchi's avatar Lucas De Marchi Committed by Rodrigo Vivi
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drm/xe: Remove GEN[0-9]*_ prefixes 



After noticing in logs there were still mentions to GEN6 registers, it
was clear commit d9b79ad2 ("drm/xe: Drop gen afixes from registers")
didn't take care of all the afixes. Some were added later, but there are
also constants and strings still using that.  Continue the cleanup
removing the remaining ones.

To keep it consistent with code nearby, a few other changes are made:

	- Remove prefix in INTEL_LEGACY_64B_CONTEXT
	- Remove GEN8_CTX_L3LLC_COHERENT since it's unused
	- Rename GEN9_FREQ_SCALER to GT_FREQUENCY_SCALER

v2: Use XELP_ as prefix for NUM_MOCS_ENTRIES and remove changes to
    MOCS_ENTRIES as this is now done as part of a previous commit
    (Matt Roper)

Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231117174049.527192-3-lucas.demarchi@intel.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 4399e951

drivers/gpu/drm/xe/xe_execlist.c

+8 −8
Original line number Diff line number Diff line
@@ -28,14 +28,14 @@ 


#define XE_EXECLIST_HANG_LIMIT 1



#define GEN11_SW_CTX_ID_SHIFT 37

#define GEN11_SW_CTX_ID_WIDTH 11

#define SW_CTX_ID_SHIFT 37

#define SW_CTX_ID_WIDTH 11

#define XEHP_SW_CTX_ID_SHIFT  39

#define XEHP_SW_CTX_ID_WIDTH  16



#define GEN11_SW_CTX_ID \

	GENMASK_ULL(GEN11_SW_CTX_ID_WIDTH + GEN11_SW_CTX_ID_SHIFT - 1, \

		    GEN11_SW_CTX_ID_SHIFT)

#define SW_CTX_ID \

	GENMASK_ULL(SW_CTX_ID_WIDTH + SW_CTX_ID_SHIFT - 1, \

		    SW_CTX_ID_SHIFT)



#define XEHP_SW_CTX_ID \

	GENMASK_ULL(XEHP_SW_CTX_ID_WIDTH + XEHP_SW_CTX_ID_SHIFT - 1, \
@@ -55,8 +55,8 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc, 
		xe_gt_assert(hwe->gt, FIELD_FIT(XEHP_SW_CTX_ID, ctx_id));

		lrc_desc |= FIELD_PREP(XEHP_SW_CTX_ID, ctx_id);

	} else {

		xe_gt_assert(hwe->gt, FIELD_FIT(GEN11_SW_CTX_ID, ctx_id));

		lrc_desc |= FIELD_PREP(GEN11_SW_CTX_ID, ctx_id);

		xe_gt_assert(hwe->gt, FIELD_FIT(SW_CTX_ID, ctx_id));

		lrc_desc |= FIELD_PREP(SW_CTX_ID, ctx_id);

	}



	if (hwe->class == XE_ENGINE_CLASS_COMPUTE)
@@ -96,7 +96,7 @@ static void __xe_execlist_port_start(struct xe_execlist_port *port, 
				     struct xe_execlist_exec_queue *exl)

{

	struct xe_device *xe = gt_to_xe(port->hwe->gt);

	int max_ctx = FIELD_MAX(GEN11_SW_CTX_ID);

	int max_ctx = FIELD_MAX(SW_CTX_ID);



	if (GRAPHICS_VERx100(xe) >= 1250)

		max_ctx = FIELD_MAX(XEHP_SW_CTX_ID);

drivers/gpu/drm/xe/xe_gt.c

+1 −1
Original line number Diff line number Diff line
@@ -515,7 +515,7 @@ static int do_gt_reset(struct xe_gt *gt) 
	xe_mmio_write32(gt, GDRST, GRDOM_FULL);

	err = xe_mmio_wait32(gt, GDRST, GRDOM_FULL, 0, 5000, NULL, false);

	if (err)

		xe_gt_err(gt, "failed to clear GEN11_GRDOM_FULL (%pe)\n",

		xe_gt_err(gt, "failed to clear GRDOM_FULL (%pe)\n",

			  ERR_PTR(err));



	return err;

drivers/gpu/drm/xe/xe_guc.c

+1 −1
Original line number Diff line number Diff line
@@ -301,7 +301,7 @@ int xe_guc_reset(struct xe_guc *guc) 


	ret = xe_mmio_wait32(gt, GDRST, GRDOM_GUC, 0, 5000, &gdrst, false);

	if (ret) {

		drm_err(&xe->drm, "GuC reset timed out, GEN6_GDRST=0x%8x\n",

		drm_err(&xe->drm, "GuC reset timed out, GDRST=0x%8x\n",

			gdrst);

		goto err_out;

	}

drivers/gpu/drm/xe/xe_guc_pc.c

+9 −9
Original line number Diff line number Diff line
@@ -23,19 +23,19 @@ 


#define MCHBAR_MIRROR_BASE_SNB	0x140000



#define GEN6_RP_STATE_CAP	XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5998)

#define RP_STATE_CAP		XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5998)

#define   RP0_MASK		REG_GENMASK(7, 0)

#define   RP1_MASK		REG_GENMASK(15, 8)

#define   RPN_MASK		REG_GENMASK(23, 16)



#define GEN10_FREQ_INFO_REC	XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)

#define FREQ_INFO_REC	XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)

#define   RPE_MASK		REG_GENMASK(15, 8)



#define GT_PERF_STATUS		XE_REG(0x1381b4)

#define   GEN12_CAGF_MASK	REG_GENMASK(19, 11)

#define   CAGF_MASK	REG_GENMASK(19, 11)



#define GT_FREQUENCY_MULTIPLIER	50

#define GEN9_FREQ_SCALER	3

#define GT_FREQUENCY_SCALER	3



/**

 * DOC: GuC Power Conservation (PC)
@@ -244,12 +244,12 @@ static int pc_action_setup_gucrc(struct xe_guc_pc *pc, u32 mode) 
static u32 decode_freq(u32 raw)

{

	return DIV_ROUND_CLOSEST(raw * GT_FREQUENCY_MULTIPLIER,

				 GEN9_FREQ_SCALER);

				 GT_FREQUENCY_SCALER);

}



static u32 encode_freq(u32 freq)

{

	return DIV_ROUND_CLOSEST(freq * GEN9_FREQ_SCALER,

	return DIV_ROUND_CLOSEST(freq * GT_FREQUENCY_SCALER,

				 GT_FREQUENCY_MULTIPLIER);

}
@@ -362,7 +362,7 @@ static void tgl_update_rpe_value(struct xe_guc_pc *pc) 
	if (xe->info.platform == XE_PVC)

		reg = xe_mmio_read32(gt, PVC_RP_STATE_CAP);

	else

		reg = xe_mmio_read32(gt, GEN10_FREQ_INFO_REC);

		reg = xe_mmio_read32(gt, FREQ_INFO_REC);



	pc->rpe_freq = REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;

}
@@ -402,7 +402,7 @@ static ssize_t freq_act_show(struct device *dev, 
		freq = REG_FIELD_GET(MTL_CAGF_MASK, freq);

	} else {

		freq = xe_mmio_read32(gt, GT_PERF_STATUS);

		freq = REG_FIELD_GET(GEN12_CAGF_MASK, freq);

		freq = REG_FIELD_GET(CAGF_MASK, freq);

	}



	ret = sysfs_emit(buf, "%d\n", decode_freq(freq));
@@ -702,7 +702,7 @@ static void tgl_init_fused_rp_values(struct xe_guc_pc *pc) 
	if (xe->info.platform == XE_PVC)

		reg = xe_mmio_read32(gt, PVC_RP_STATE_CAP);

	else

		reg = xe_mmio_read32(gt, GEN6_RP_STATE_CAP);

		reg = xe_mmio_read32(gt, RP_STATE_CAP);

	pc->rp0_freq = REG_FIELD_GET(RP0_MASK, reg) * GT_FREQUENCY_MULTIPLIER;

	pc->rpn_freq = REG_FIELD_GET(RPN_MASK, reg) * GT_FREQUENCY_MULTIPLIER;

}

drivers/gpu/drm/xe/xe_lrc.c

+11 −12
Original line number Diff line number Diff line
@@ -23,14 +23,13 @@ 
#include "xe_map.h"

#include "xe_vm.h"



#define GEN8_CTX_VALID				(1 << 0)

#define GEN8_CTX_L3LLC_COHERENT			(1 << 5)

#define GEN8_CTX_PRIVILEGE			(1 << 8)

#define GEN8_CTX_ADDRESSING_MODE_SHIFT		3

#define INTEL_LEGACY_64B_CONTEXT		3

#define CTX_VALID				(1 << 0)

#define CTX_PRIVILEGE				(1 << 8)

#define CTX_ADDRESSING_MODE_SHIFT		3

#define LEGACY_64B_CONTEXT			3



#define GEN11_ENGINE_CLASS_SHIFT		61

#define GEN11_ENGINE_INSTANCE_SHIFT		48

#define ENGINE_CLASS_SHIFT			61

#define ENGINE_INSTANCE_SHIFT			48



static struct xe_device *

lrc_to_xe(struct xe_lrc *lrc)
@@ -765,19 +764,19 @@ int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe, 
				     (q->usm.acc_notify << ACC_NOTIFY_S) |

				     q->usm.acc_trigger);



	lrc->desc = GEN8_CTX_VALID;

	lrc->desc |= INTEL_LEGACY_64B_CONTEXT << GEN8_CTX_ADDRESSING_MODE_SHIFT;

	lrc->desc = CTX_VALID;

	lrc->desc |= LEGACY_64B_CONTEXT << CTX_ADDRESSING_MODE_SHIFT;

	/* TODO: Priority */



	/* While this appears to have something about privileged batches or

	 * some such, it really just means PPGTT mode.

	 */

	if (vm)

		lrc->desc |= GEN8_CTX_PRIVILEGE;

		lrc->desc |= CTX_PRIVILEGE;



	if (GRAPHICS_VERx100(xe) < 1250) {

		lrc->desc |= (u64)hwe->instance << GEN11_ENGINE_INSTANCE_SHIFT;

		lrc->desc |= (u64)hwe->class << GEN11_ENGINE_CLASS_SHIFT;

		lrc->desc |= (u64)hwe->instance << ENGINE_INSTANCE_SHIFT;

		lrc->desc |= (u64)hwe->class << ENGINE_CLASS_SHIFT;

	}



	arb_enable = MI_ARB_ON_OFF | MI_ARB_ENABLE;