Commit 0bdd29f5 authored by Ankit Nautiyal's avatar Ankit Nautiyal
Browse files

drm/i915/dp: Refactor dsc_slice_count handling in intel_dp_mode_valid()



Make dsc_slice_count closer to the block where it is used and promote it
from u8 to int. This aligns it with upcoming DSC bubble pixel-rate
adjustments, where the slice count participates in wider arithmetic.

Currently, for non-eDP (DP/DP_MST) cases  the slice count is computed only
inside intel_dp_dsc_mode_valid() and is not used by the caller. Once DSC
bubble handling is added, dp_mode_valid() will need access to its own local
slice count for non-eDP cases as well.

Signed-off-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20260202103731.357416-14-ankit.k.nautiyal@intel.com
parent 7a687f70
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+7 −7
Original line number Diff line number Diff line
@@ -1436,7 +1436,6 @@ intel_dp_mode_valid(struct drm_connector *_connector,
	int target_clock = mode->clock;
	int max_rate, mode_rate, max_lanes, max_link_clock;
	u16 dsc_max_compressed_bpp = 0;
	u8 dsc_slice_count = 0;
	enum drm_mode_status status;
	bool dsc = false;
	int num_joined_pipes;
@@ -1486,6 +1485,8 @@ intel_dp_mode_valid(struct drm_connector *_connector,
	 */
	status = MODE_CLOCK_HIGH;
	for (num_joined_pipes = 1; num_joined_pipes <= I915_MAX_PIPES; num_joined_pipes++) {
		int dsc_slice_count = 0;

		if (connector->force_joined_pipes &&
		    num_joined_pipes != connector->force_joined_pipes)
			continue;
@@ -1503,6 +1504,11 @@ intel_dp_mode_valid(struct drm_connector *_connector,
		if (intel_dp_has_dsc(connector)) {
			int pipe_bpp;

			dsc_slice_count = intel_dp_dsc_get_slice_count(connector,
								       target_clock,
								       mode->hdisplay,
								       num_joined_pipes);

			/*
			 * TBD pass the connector BPC,
			 * for now U8_MAX so that max BPC on that platform would be picked
@@ -1517,12 +1523,6 @@ intel_dp_mode_valid(struct drm_connector *_connector,
				dsc_max_compressed_bpp =
					drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;

				dsc_slice_count =
					intel_dp_dsc_get_slice_count(connector,
								     target_clock,
								     mode->hdisplay,
								     num_joined_pipes);

				dsc = dsc_max_compressed_bpp && dsc_slice_count;
			} else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
				unsigned long bw_overhead_flags = 0;