Commit 0c1f1eb6 authored by Russell King (Oracle)'s avatar Russell King (Oracle) Committed by Paolo Abeni
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net: stmmac: allow platforms to use PHY tx clock stop capability



Allow platform glue to instruct stmmac to make use of the PHY transmit
clock stop capability when deciding whether to allow the transmit clock
from the DWMAC core to be stopped.

Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1tsITp-005vG9-Px@rmk-PC.armlinux.org.uk


Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent 4df2ebfc
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+1 −0
Original line number Diff line number Diff line
@@ -306,6 +306,7 @@ struct stmmac_priv {
	struct timer_list eee_ctrl_timer;
	int lpi_irq;
	u32 tx_lpi_timer;
	bool tx_lpi_clk_stop;
	bool eee_enabled;
	bool eee_active;
	bool eee_sw_timer_en;
+12 −4
Original line number Diff line number Diff line
@@ -457,8 +457,7 @@ static void stmmac_try_to_start_sw_lpi(struct stmmac_priv *priv)
	/* Check and enter in LPI mode */
	if (!priv->tx_path_in_lpi_mode)
		stmmac_set_lpi_mode(priv, priv->hw, STMMAC_LPI_FORCED,
			priv->plat->flags & STMMAC_FLAG_EN_TX_LPI_CLOCKGATING,
			0);
				    priv->tx_lpi_clk_stop, 0);
}

/**
@@ -1104,13 +1103,18 @@ static int stmmac_mac_enable_tx_lpi(struct phylink_config *config, u32 timer,

	priv->eee_enabled = true;

	/* Update the transmit clock stop according to PHY capability if
	 * the platform allows
	 */
	if (priv->plat->flags & STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP)
		priv->tx_lpi_clk_stop = tx_clk_stop;

	stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
			     STMMAC_DEFAULT_TWT_LS);

	/* Try to cnfigure the hardware timer. */
	ret = stmmac_set_lpi_mode(priv, priv->hw, STMMAC_LPI_TIMER,
				  priv->plat->flags & STMMAC_FLAG_EN_TX_LPI_CLOCKGATING,
				  priv->tx_lpi_timer);
				  priv->tx_lpi_clk_stop, priv->tx_lpi_timer);

	if (ret) {
		/* Hardware timer mode not supported, or value out of range.
@@ -1269,6 +1273,10 @@ static int stmmac_phy_setup(struct stmmac_priv *priv)
	if (!(priv->plat->flags & STMMAC_FLAG_RX_CLK_RUNS_IN_LPI))
		priv->phylink_config.eee_rx_clk_stop_enable = true;

	/* Set the default transmit clock stop bit based on the platform glue */
	priv->tx_lpi_clk_stop = priv->plat->flags &
				STMMAC_FLAG_EN_TX_LPI_CLOCKGATING;

	mdio_bus_data = priv->plat->mdio_bus_data;
	if (mdio_bus_data)
		priv->phylink_config.default_an_inband =
+2 −1
Original line number Diff line number Diff line
@@ -183,7 +183,8 @@ struct dwmac4_addrs {
#define STMMAC_FLAG_INT_SNAPSHOT_EN		BIT(9)
#define STMMAC_FLAG_RX_CLK_RUNS_IN_LPI		BIT(10)
#define STMMAC_FLAG_EN_TX_LPI_CLOCKGATING	BIT(11)
#define STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY	BIT(12)
#define STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP	BIT(12)
#define STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY	BIT(13)

struct plat_stmmacenet_data {
	int bus_id;