Commit 0c3f9723 authored by Jesse Zhang's avatar Jesse Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: Add soft reset callback to SDMA v4.4.x 



Implement soft reset engine callback for SDMA 4.4.x IPs. This avoids IP
version check in generic implementation.

V2: Correct physical instance ID calculation in soft_reset_engine (Jesse)

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarJesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3bab282d

drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c

+4 −30
Original line number Diff line number Diff line
@@ -534,37 +534,11 @@ bool amdgpu_sdma_is_shared_inv_eng(struct amdgpu_device *adev, struct amdgpu_rin 
static int amdgpu_sdma_soft_reset(struct amdgpu_device *adev, u32 instance_id)

{

	struct amdgpu_sdma_instance *sdma_instance = &adev->sdma.instance[instance_id];

	int r = -EOPNOTSUPP;



	switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {

	case IP_VERSION(4, 4, 2):

	case IP_VERSION(4, 4, 4):

	case IP_VERSION(4, 4, 5):

		/* For SDMA 4.x, use the existing DPM interface for backward compatibility,

		 * we need to convert the logical instance ID to physical instance ID before reset.

		 */

		r = amdgpu_dpm_reset_sdma(adev, 1 << GET_INST(SDMA0, instance_id));

		break;

	case IP_VERSION(5, 0, 0):

	case IP_VERSION(5, 0, 1):

	case IP_VERSION(5, 0, 2):

	case IP_VERSION(5, 0, 5):

	case IP_VERSION(5, 2, 0):

	case IP_VERSION(5, 2, 2):

	case IP_VERSION(5, 2, 4):

	case IP_VERSION(5, 2, 5):

	case IP_VERSION(5, 2, 6):

	case IP_VERSION(5, 2, 3):

	case IP_VERSION(5, 2, 1):

	case IP_VERSION(5, 2, 7):



	if (sdma_instance->funcs->soft_reset_kernel_queue)

			r = sdma_instance->funcs->soft_reset_kernel_queue(adev, instance_id);

		break;

	default:

		break;

	}

		return sdma_instance->funcs->soft_reset_kernel_queue(adev, instance_id);



	return r;

	return -EOPNOTSUPP;

}



/**

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

+12 −0
Original line number Diff line number Diff line
@@ -109,6 +109,8 @@ static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev); 
static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev);

static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring);

static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring);

static int sdma_v4_4_2_soft_reset_engine(struct amdgpu_device *adev,

					 u32 instance_id);



static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev,

		u32 instance, u32 offset)
@@ -1337,6 +1339,7 @@ static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev) 
static const struct amdgpu_sdma_funcs sdma_v4_4_2_sdma_funcs = {

	.stop_kernel_queue = &sdma_v4_4_2_stop_queue,

	.start_kernel_queue = &sdma_v4_4_2_restore_queue,

	.soft_reset_kernel_queue = &sdma_v4_4_2_soft_reset_engine,

};



static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block)
@@ -1745,6 +1748,15 @@ static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring) 
	return sdma_v4_4_2_inst_start(adev, inst_mask, true);

}



static int sdma_v4_4_2_soft_reset_engine(struct amdgpu_device *adev,

					 u32 instance_id)

{

	/* For SDMA 4.x, use the existing DPM interface for backward compatibility

	 * we need to convert the logical instance ID to physical instance ID before reset.

	 */

	return amdgpu_dpm_reset_sdma(adev, 1 << GET_INST(SDMA0, instance_id));

}



static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev,

					struct amdgpu_irq_src *source,

					unsigned type,