Commit 0c5caea7 authored by Dapeng Mi's avatar Dapeng Mi Committed by Peter Zijlstra
Browse files

perf/x86: Add PERF_CAP_PEBS_TIMING_INFO flag 



IA32_PERF_CAPABILITIES.PEBS_TIMING_INFO[bit 17] is introduced to
indicate whether timed PEBS is supported. Timed PEBS adds a new "retired
latency" field in basic info group to show the timing info. Please find
detailed information about timed PEBS in section 8.4.1 "Timed Processor
Event Based Sampling" of "Intel Architecture Instruction Set Extensions
and Future Features".

This patch adds PERF_CAP_PEBS_TIMING_INFO flag and KVM module leverages
this flag to expose timed PEBS feature to guest.

Moreover, opportunistically refine the indents and make the macros
share consistent indents.

Signed-off-by: default avatarDapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Tested-by: default avatarYi Lai <yi1.lai@intel.com>
Link: https://lore.kernel.org/r/20250820023032.17128-5-dapeng1.mi@linux.intel.com
parent 43796f30

arch/x86/include/asm/msr-index.h

+8 −6
Original line number Diff line number Diff line
@@ -319,8 +319,10 @@ 
#define PERF_CAP_ARCH_REG		BIT_ULL(7)

#define PERF_CAP_PEBS_FORMAT		0xf00

#define PERF_CAP_PEBS_BASELINE		BIT_ULL(14)

#define PERF_CAP_PEBS_TIMING_INFO	BIT_ULL(17)

#define PERF_CAP_PEBS_MASK		(PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \

				 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE)

					 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \

					 PERF_CAP_PEBS_TIMING_INFO)



#define MSR_IA32_RTIT_CTL		0x00000570

#define RTIT_CTL_TRACEEN		BIT(0)

tools/arch/x86/include/asm/msr-index.h

+8 −6
Original line number Diff line number Diff line
@@ -319,8 +319,10 @@ 
#define PERF_CAP_ARCH_REG		BIT_ULL(7)

#define PERF_CAP_PEBS_FORMAT		0xf00

#define PERF_CAP_PEBS_BASELINE		BIT_ULL(14)

#define PERF_CAP_PEBS_TIMING_INFO	BIT_ULL(17)

#define PERF_CAP_PEBS_MASK		(PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \

				 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE)

					 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \

					 PERF_CAP_PEBS_TIMING_INFO)



#define MSR_IA32_RTIT_CTL		0x00000570

#define RTIT_CTL_TRACEEN		BIT(0)