Commit 0cbc0258 authored by Tom Lendacky's avatar Tom Lendacky Committed by Borislav Petkov (AMD)
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x86/sev: Add support for the RMPREAD instruction 



The RMPREAD instruction returns an architecture defined format of an
RMP table entry. This is the preferred method for examining RMP entries.

The instruction is advertised in CPUID 0x8000001f_EAX[21]. Use this
instruction when available.

Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: default avatarNikunj A Dadhania <nikunj@amd.com>
Reviewed-by: default avatarNeeraj Upadhyay <Neeraj.Upadhyay@amd.com>
Reviewed-by: default avatarAshish Kalra <ashish.kalra@amd.com>
Link: https://lore.kernel.org/r/72c734ac8b324bbc0c839b2c093a11af4a8881fa.1733172653.git.thomas.lendacky@amd.com
parent 3e43c60e

arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -451,6 +451,7 @@ 
#define X86_FEATURE_V_TSC_AUX		(19*32+ 9) /* Virtual TSC_AUX */

#define X86_FEATURE_SME_COHERENT	(19*32+10) /* AMD hardware-enforced cache coherency */

#define X86_FEATURE_DEBUG_SWAP		(19*32+14) /* "debug_swap" AMD SEV-ES full debug state swap support */

#define X86_FEATURE_RMPREAD		(19*32+21) /* RMPREAD instruction */

#define X86_FEATURE_SVSM		(19*32+28) /* "svsm" SVSM present */



/* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */

arch/x86/virt/svm/sev.c

+12 −0
Original line number Diff line number Diff line
@@ -306,6 +306,18 @@ static int get_rmpentry(u64 pfn, struct rmpentry *e) 
{

	struct rmpentry_raw *e_raw;



	if (cpu_feature_enabled(X86_FEATURE_RMPREAD)) {

		int ret;



		/* Binutils version 2.44 supports the RMPREAD mnemonic. */

		asm volatile(".byte 0xf2, 0x0f, 0x01, 0xfd"

			     : "=a" (ret)

			     : "a" (pfn << PAGE_SHIFT), "c" (e)

			     : "memory", "cc");



		return ret;

	}



	e_raw = get_raw_rmpentry(pfn);

	if (IS_ERR(e_raw))

		return PTR_ERR(e_raw);