Commit 0cc0c5e7 authored by Tim Huang's avatar Tim Huang Committed by Alex Deucher
Browse files

drm/amdgpu: add support for NBIO IP version 7.11.4 



This initializes NBIO IP version 7.11.4.

Reviewed-by: default avatarMario Limonciello <mario.limonciello@amd.com>
Signed-off-by: default avatarTim Huang <tim.huang@amd.com>
Signed-off-by: default avatarPratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ab90fd05

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

+1 −0
Original line number Diff line number Diff line
@@ -3065,6 +3065,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
		adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg;

		break;

	case IP_VERSION(6, 3, 1):

	case IP_VERSION(7, 11, 4):

		adev->nbio.funcs = &nbif_v6_3_1_funcs;

		adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg;

		break;

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

+63 −10
Original line number Diff line number Diff line
@@ -30,6 +30,31 @@ 
#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"

#include <uapi/linux/kfd_ioctl.h>



#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10                                                           0x4f0aeb

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10_BASE_IDX                                                  3

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_nbif_4_10                                                          0x4f0aec

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_nbif_4_10_BASE_IDX                                                 3

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10                                                           0x4f0aed

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10_BASE_IDX                                                  3

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_nbif_4_10                                                          0x4f0aee

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_nbif_4_10_BASE_IDX                                                 3

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10                                                           0x4f0aef

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10_BASE_IDX                                                  3

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_nbif_4_10                                                          0x4f0af0

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_nbif_4_10_BASE_IDX                                                 3

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10                                                           0x4f0af1

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10_BASE_IDX                                                  3

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_nbif_4_10                                                          0x4f0af2

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_nbif_4_10_BASE_IDX                                                 3

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10                                                           0x4f0af3

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10_BASE_IDX                                                  3

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_nbif_4_10                                                          0x4f0af4

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_nbif_4_10_BASE_IDX                                                 3

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10                                                           0x4f0af5

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10_BASE_IDX                                                  3

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_nbif_4_10                                                          0x4f0af6

#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_nbif_4_10_BASE_IDX                                                 3



static void nbif_v6_3_1_remap_hdp_registers(struct amdgpu_device *adev)

{

	WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
@@ -98,9 +123,13 @@ static void nbif_v6_3_1_sdma_doorbell_range(struct amdgpu_device *adev, 
						       S2A_DOORBELL_PORT2_RANGE_SIZE,

						       0);



		if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) {

			WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10, doorbell_range);

		} else {

			WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, doorbell_range);

		}

	}

}



static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev,

					   bool use_doorbell, int doorbell_index,
@@ -140,17 +169,29 @@ static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev, 
					       S2A_DOORBELL_PORT4_RANGE_SIZE,

					       0);



	if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) {

		if (instance)

			WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10, doorbell_range);

		else

			WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10, doorbell_range);

	} else {

		if (instance)

			WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range);

		else

			WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, doorbell_range);

	}

}



static void nbif_v6_3_1_gc_doorbell_init(struct amdgpu_device *adev)

{

	if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) {

		WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10, 0x30000007);

		WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10, 0x3000000d);

	} else {

		WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007);

		WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d);

	}

}



static void nbif_v6_3_1_enable_doorbell_aperture(struct amdgpu_device *adev,

						 bool enable)
@@ -214,8 +255,12 @@ static void nbif_v6_3_1_ih_doorbell_range(struct amdgpu_device *adev, 
						  S2A_DOORBELL_PORT1_RANGE_SIZE,

						  0);



	if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) {

		WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10, ih_doorbell_range);

	} else {

		WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range);

	}

}



static void nbif_v6_3_1_ih_control(struct amdgpu_device *adev)

{
@@ -269,11 +314,19 @@ static u32 nbif_v6_3_1_get_hdp_flush_done_offset(struct amdgpu_device *adev) 


static u32 nbif_v6_3_1_get_pcie_index_offset(struct amdgpu_device *adev)

{

	if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) {

		return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX);

	}

	else {

		return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);

	}

}



static u32 nbif_v6_3_1_get_pcie_data_offset(struct amdgpu_device *adev)

{

	if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4))

		return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA);

	else

		return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);

}

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

+1 −0
Original line number Diff line number Diff line
@@ -279,6 +279,7 @@ static void nbio_v7_11_init_registers(struct amdgpu_device *adev) 
	case IP_VERSION(7, 11, 1):

	case IP_VERSION(7, 11, 2):

	case IP_VERSION(7, 11, 3):

	case IP_VERSION(7, 11, 4):

		data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4) & ~BIT(23);

		WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4, data);

		break;

drivers/gpu/drm/amd/amdgpu/soc21.c

+1 −0
Original line number Diff line number Diff line
@@ -965,6 +965,7 @@ static int soc21_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 
	case IP_VERSION(7, 11, 1):

	case IP_VERSION(7, 11, 2):

	case IP_VERSION(7, 11, 3):

	case IP_VERSION(7, 11, 4):

		adev->nbio.funcs->update_medium_grain_clock_gating(adev,

				state == AMD_CG_STATE_GATE);

		adev->nbio.funcs->update_medium_grain_light_sleep(adev,