Commit 0cc88243 authored by Jocelyn Falempe's avatar Jocelyn Falempe Committed by Maarten Lankhorst
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drm/i915/display: Add drm_panic support for 4-tiling with DPT 



On Alder Lake and later, it's not possible to disable tiling when DPT
is enabled.
So this commit implements 4-Tiling support, to still be able to draw
the panic screen.

Signed-off-by: default avatarJocelyn Falempe <jfalempe@redhat.com>
Link: https://lore.kernel.org/r/20250624091501.257661-11-jfalempe@redhat.com


Signed-off-by: default avatarMaarten Lankhorst <dev@lankhorst.se>
parent 116d86dd

drivers/gpu/drm/i915/display/intel_plane.c

+20 −0
Original line number Diff line number Diff line
@@ -1298,6 +1298,25 @@ static unsigned int intel_ytile_get_offset(unsigned int width, unsigned int x, u 
	return offset;

}



static unsigned int intel_4tile_get_offset(unsigned int width, unsigned int x, unsigned int y)

{

	u32 offset;

	unsigned int swizzle;

	unsigned int width_in_blocks = DIV_ROUND_UP(width, 32);



	/* Block offset */

	offset = ((y / YTILE_HEIGHT) * width_in_blocks + (x / YTILE_WIDTH)) * YTILE_SIZE;



	x = x % YTILE_WIDTH;

	y = y % YTILE_HEIGHT;



	/* bit order inside a block is y4 y3 x4 y2 x3 x2 y1 y0 x1 x0 */

	swizzle = (x & 3) | ((y & 3) << 2) | ((x & 0xc) << 2) | (y & 4) << 4 |

		  ((x & 0x10) << 3) | ((y & 0x18) << 5);

	offset += swizzle * 4;

	return offset;

}



static void intel_panic_flush(struct drm_plane *plane)

{

	struct intel_plane_state *plane_state = to_intel_plane_state(plane->state);
@@ -1341,6 +1360,7 @@ static unsigned int (*intel_get_tiling_func(u64 fb_modifier))(unsigned int width 
	case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:

	case I915_FORMAT_MOD_4_TILED_BMG_CCS:

	case I915_FORMAT_MOD_4_TILED_LNL_CCS:

		return intel_4tile_get_offset;

	case I915_FORMAT_MOD_X_TILED:

	case I915_FORMAT_MOD_Yf_TILED:

	case I915_FORMAT_MOD_Yf_TILED_CCS: