Commit 0d02e8d2 authored by Alexander Shiyan's avatar Alexander Shiyan Committed by Heiko Stuebner
Browse files

clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_p 



The 32kHz input clock is named "xin32k" in the driver,
so the name "32k" appears to be a typo in this case. Lets fix this.

Signed-off-by: default avatarAlexander Shiyan <eagle.alexander923@gmail.com>
Reviewed-by: default avatarDragan Simic <dsimic@manjaro.org>
Fixes: f1c506d1 ("clk: rockchip: add clock controller for the RK3588")
Link: https://lore.kernel.org/r/20240829052820.3604-1-eagle.alexander923@gmail.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent fb234516

drivers/clk/rockchip/clk-rk3588.c

+1 −1
Original line number Diff line number Diff line
@@ -526,7 +526,7 @@ PNAME(pmu_200m_100m_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src" }; 
PNAME(pmu_300m_24m_p)			= { "clk_300m_src", "xin24m" };

PNAME(pmu_400m_24m_p)			= { "clk_400m_src", "xin24m" };

PNAME(pmu_100m_50m_24m_src_p)		= { "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" };

PNAME(pmu_24m_32k_100m_src_p)		= { "xin24m", "32k", "clk_pmu1_100m_src" };

PNAME(pmu_24m_32k_100m_src_p)		= { "xin24m", "xin32k", "clk_pmu1_100m_src" };

PNAME(hclk_pmu1_root_p)			= { "clk_pmu1_200m_src", "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" };

PNAME(hclk_pmu_cm0_root_p)		= { "clk_pmu1_400m_src", "clk_pmu1_200m_src", "clk_pmu1_100m_src", "xin24m" };

PNAME(mclk_pdm0_p)			= { "clk_pmu1_300m_src", "clk_pmu1_200m_src" };