Commit 0d5b288c authored by Tim Harvey's avatar Tim Harvey Committed by Shawn Guo
Browse files

arm64: dts: freescale: Add imx8mp-venice-gw7905-2x 



The Gateworks imx8mp-venice-gw7905-2x consists of a SOM + baseboard.

The GW702x SOM contains the following:
 - i.MX8M Plus SoC
 - LPDDR4 memory
 - eMMC Boot device
 - Gateworks System Controller (GSC) with integrated EEPROM, button
   controller, and ADC's
 - PMIC
 - RGMII PHY (eQoS)
 - SOM connector providing:
  - eQoS GbE MII
  - 1x SPI
  - 2x I2C
  - 4x UART
  - 2x USB 3.0
  - 1x PCI
  - 1x SDIO (4-bit 3.3V)
  - 1x SDIO (4-bit 3.3V/1.8V)
  - GPIO

The GW7905 Baseboard contains the following:
 - GPS
 - microSD
 - off-board I/O connector with I2C, SPI, GPIO
 - EERPOM
 - PCIe clock generator
 - 1x full-length miniPCIe socket with PCI/USB3 (via mux) and USB2.0
 - 1x half-length miniPCIe socket with USB2.0 and USB3.0
 - USB 3.0 HUB
 - USB Type-C with USB PD Sink capability and peripheral support
 - USB Type-C with USB 3.0 host support

Signed-off-by: default avatarTim Harvey <tharvey@gateworks.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 20d0b83e

arch/arm64/boot/dts/freescale/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb 
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw7905-2x.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-yavia.dtb

arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi

0 → 100644
+587 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Copyright 2023 Gateworks Corporation

 */



#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/input/linux-event-codes.h>

#include <dt-bindings/net/ti-dp83867.h>



/ {

	aliases {

		ethernet0 = &eqos;

	};



	memory@40000000 {

		device_type = "memory";

		reg = <0x0 0x40000000 0 0x80000000>;

	};



	gpio-keys {

		compatible = "gpio-keys";



		key-user-pb {

			label = "user_pb";

			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;

			linux,code = <BTN_0>;

		};



		key-user-pb1x {

			label = "user_pb1x";

			linux,code = <BTN_1>;

			interrupt-parent = <&gsc>;

			interrupts = <0>;

		};



		key-erased {

			label = "key_erased";

			linux,code = <BTN_2>;

			interrupt-parent = <&gsc>;

			interrupts = <1>;

		};



		key-eeprom-wp {

			label = "eeprom_wp";

			linux,code = <BTN_3>;

			interrupt-parent = <&gsc>;

			interrupts = <2>;

		};



		key-tamper {

			label = "tamper";

			linux,code = <BTN_4>;

			interrupt-parent = <&gsc>;

			interrupts = <5>;

		};



		switch-hold {

			label = "switch_hold";

			linux,code = <BTN_5>;

			interrupt-parent = <&gsc>;

			interrupts = <7>;

		};

	};

};



&A53_0 {

	cpu-supply = <&buck3_reg>;

};



&A53_1 {

	cpu-supply = <&buck3_reg>;

};



&A53_2 {

	cpu-supply = <&buck3_reg>;

};



&A53_3 {

	cpu-supply = <&buck3_reg>;

};



&eqos {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_eqos>;

	phy-mode = "rgmii-id";

	phy-handle = <&ethphy0>;

	status = "okay";



	mdio {

		compatible = "snps,dwmac-mdio";

		#address-cells = <1>;

		#size-cells = <0>;



		ethphy0: ethernet-phy@0 {

			compatible = "ethernet-phy-ieee802.3-c22";

			pinctrl-0 = <&pinctrl_ethphy0>;

			pinctrl-names = "default";

			reg = <0x0>;

			interrupt-parent = <&gpio3>;

			interrupts = <16 IRQ_TYPE_EDGE_FALLING>;

			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;

			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;

			tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;

			rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;

		};

	};

};



&i2c1 {

	clock-frequency = <100000>;

	pinctrl-names = "default", "gpio";

	pinctrl-0 = <&pinctrl_i2c1>;

	pinctrl-1 = <&pinctrl_i2c1_gpio>;

	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	status = "okay";



	gsc: gsc@20 {

		compatible = "gw,gsc";

		reg = <0x20>;

		pinctrl-0 = <&pinctrl_gsc>;

		interrupt-parent = <&gpio2>;

		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;

		interrupt-controller;

		#interrupt-cells = <1>;

		#address-cells = <1>;

		#size-cells = <0>;



		adc {

			compatible = "gw,gsc-adc";

			#address-cells = <1>;

			#size-cells = <0>;



			channel@6 {

				gw,mode = <0>;

				reg = <0x06>;

				label = "temp";

			};



			channel@8 {

				gw,mode = <1>;

				reg = <0x08>;

				label = "vdd_bat";

			};



			channel@16 {

				gw,mode = <4>;

				reg = <0x16>;

				label = "fan_tach";

			};



			channel@82 {

				gw,mode = <2>;

				reg = <0x82>;

				label = "vdd_vin";

				gw,voltage-divider-ohms = <22100 1000>;

			};



			channel@84 {

				gw,mode = <2>;

				reg = <0x84>;

				label = "vdd_adc1";

				gw,voltage-divider-ohms = <10000 10000>;

			};



			channel@86 {

				gw,mode = <2>;

				reg = <0x86>;

				label = "vdd_adc2";

				gw,voltage-divider-ohms = <10000 10000>;

			};



			channel@88 {

				gw,mode = <2>;

				reg = <0x88>;

				label = "vdd_1p0";

			};



			channel@8c {

				gw,mode = <2>;

				reg = <0x8c>;

				label = "vdd_1p8";

			};



			channel@8e {

				gw,mode = <2>;

				reg = <0x8e>;

				label = "vdd_2p5";

			};



			channel@90 {

				gw,mode = <2>;

				reg = <0x90>;

				label = "vdd_3p3";

				gw,voltage-divider-ohms = <10000 10000>;

			};



			channel@92 {

				gw,mode = <2>;

				reg = <0x92>;

				label = "vdd_dram";

			};



			channel@98 {

				gw,mode = <2>;

				reg = <0x98>;

				label = "vdd_soc";

			};



			channel@9a {

				gw,mode = <2>;

				reg = <0x9a>;

				label = "vdd_arm";

			};



			channel@a2 {

				gw,mode = <2>;

				reg = <0xa2>;

				label = "vdd_gsc";

				gw,voltage-divider-ohms = <10000 10000>;

			};

		};



		fan-controller@0 {

			compatible = "gw,gsc-fan";

			reg = <0x0a>;

		};

	};



	gpio: gpio@23 {

		compatible = "nxp,pca9555";

		reg = <0x23>;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-parent = <&gsc>;

		interrupts = <4>;

	};



	eeprom@50 {

		compatible = "atmel,24c02";

		reg = <0x50>;

		pagesize = <16>;

	};



	eeprom@51 {

		compatible = "atmel,24c02";

		reg = <0x51>;

		pagesize = <16>;

	};



	eeprom@52 {

		compatible = "atmel,24c02";

		reg = <0x52>;

		pagesize = <16>;

	};



	eeprom@53 {

		compatible = "atmel,24c02";

		reg = <0x53>;

		pagesize = <16>;

	};



	rtc@68 {

		compatible = "dallas,ds1672";

		reg = <0x68>;

	};



	pmic@69 {

		compatible = "mps,mp5416";

		reg = <0x69>;



		regulators {

			/* vdd_soc */

			buck1 {

				regulator-name = "buck1";

				regulator-min-microvolt = <850000>;

				regulator-max-microvolt = <1000000>;

				regulator-always-on;

				regulator-boot-on;

			};



			/* vdd_dram */

			buck2 {

				regulator-name = "buck2";

				regulator-min-microvolt = <1100000>;

				regulator-max-microvolt = <1100000>;

				regulator-always-on;

				regulator-boot-on;

			};



			/* vdd_arm */

			buck3_reg: buck3 {

				regulator-name = "buck3";

				regulator-min-microvolt = <850000>;

				regulator-max-microvolt = <1000000>;

				regulator-always-on;

				regulator-boot-on;

			};



			/* vdd_1p8 */

			buck4 {

				regulator-name = "buck4";

				regulator-min-microvolt = <1800000>;

				regulator-max-microvolt = <1800000>;

				regulator-always-on;

				regulator-boot-on;

			};



			/* OUT2: nvcc_snvs_1p8 */

			ldo1 {

				regulator-name = "ldo1";

				regulator-min-microvolt = <1800000>;

				regulator-max-microvolt = <1800000>;

				regulator-always-on;

				regulator-boot-on;

			};



			/* OUT3: vdd_1p0 */

			ldo2 {

				regulator-name = "ldo2";

				regulator-min-microvolt = <1000000>;

				regulator-max-microvolt = <1000000>;

				regulator-always-on;

				regulator-boot-on;

			};



			/* OUT4: vdd_2p5 */

			ldo3 {

				regulator-name = "ldo3";

				regulator-min-microvolt = <2500000>;

				regulator-max-microvolt = <2500000>;

				regulator-always-on;

				regulator-boot-on;

			};



			/* OUT5: vdd_3p3 */

			ldo4 {

				regulator-name = "ldo4";

				regulator-min-microvolt = <3300000>;

				regulator-max-microvolt = <3300000>;

				regulator-always-on;

				regulator-boot-on;

			};

		};

	};

};



/* off-board header */

&i2c2 {

	clock-frequency = <400000>;

	pinctrl-names = "default", "gpio";

	pinctrl-0 = <&pinctrl_i2c2>;

	pinctrl-1 = <&pinctrl_i2c2_gpio>;

	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	status = "okay";



	eeprom@52 {

		compatible = "atmel,24c32";

		reg = <0x52>;

		pagesize = <32>;

	};

};



/* off-board header */

&i2c3 {

	clock-frequency = <400000>;

	pinctrl-names = "default", "gpio";

	pinctrl-0 = <&pinctrl_i2c3>;

	pinctrl-1 = <&pinctrl_i2c3_gpio>;

	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	status = "okay";

};



/* off-board header */

&uart1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart1>;

	status = "okay";

};



/* console */

&uart2 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart2>;

	status = "okay";

};



/* off-board header */

&uart3 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart3>;

	status = "okay";

};



/* off-board */

&usdhc1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usdhc1>;

	bus-width = <4>;

	non-removable;

	status = "okay";

	bus-width = <4>;

	non-removable;

	status = "okay";

};



/* eMMC */

&usdhc3 {

	pinctrl-names = "default", "state_100mhz", "state_200mhz";

	pinctrl-0 = <&pinctrl_usdhc3>;

	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;

	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;

	bus-width = <8>;

	non-removable;

	status = "okay";

};



&wdog1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_wdog>;

	fsl,ext-reset-output;

	status = "okay";

};



&iomuxc {

	pinctrl_eqos: eqosgrp {

		fsl,pins = <

			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC			0x2

			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO			0x2

			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x90

			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x90

			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x90

			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x90

			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90

			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90

			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x16

			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x16

			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x16

			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x16

			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x16

			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16

		>;

	};



	pinctrl_ethphy0: ethphy0grp {

		fsl,pins = <

			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14	0x140 /* RST# */

			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x150 /* IRQ# */

		>;

	};



	pinctrl_gsc: gscgrp {

		fsl,pins = <

			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x150 /* IRQ# */

		>;

	};



	pinctrl_i2c1: i2c1grp {

		fsl,pins = <

			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2

			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2

		>;

	};



	pinctrl_i2c1_gpio: i2c1gpiogrp {

		fsl,pins = <

			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14	0x400001c2

			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15	0x400001c2

		>;

	};



	pinctrl_i2c2: i2c2grp {

		fsl,pins = <

			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2

			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2

		>;

	};



	pinctrl_i2c2_gpio: i2c2gpiogrp {

		fsl,pins = <

			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x400001c2

			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x400001c2

		>;

	};



	pinctrl_i2c3: i2c3grp {

		fsl,pins = <

			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2

			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2

		>;

	};



	pinctrl_i2c3_gpio: i2c3gpiogrp {

		fsl,pins = <

			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18	0x400001c2

			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19	0x400001c2

		>;

	};



	pinctrl_uart1: uart1grp {

		fsl,pins = <

			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140

			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140

		>;

	};



	pinctrl_uart2: uart2grp {

		fsl,pins = <

			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140

			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140

		>;

	};



	pinctrl_uart3: uart3grp {

		fsl,pins = <

			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX	0x140

			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX	0x140

		>;

	};



	pinctrl_usdhc1: usdhc1grp {

		fsl,pins = <

			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190

			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0

			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0

			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0

			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0

			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0

		>;

	};



	pinctrl_usdhc3: usdhc3grp {

		fsl,pins = <

			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190

			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0

			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0

			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0

			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0

			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0

			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0

			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0

			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0

			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0

			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190

		>;

	};



	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {

		fsl,pins = <

			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194

			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4

			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4

			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4

			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4

			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4

			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4

			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4

			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4

			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4

			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194

		>;

	};



	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {

		fsl,pins = <

			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196

			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6

			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6

			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6

			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6

			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6

			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6

			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6

			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6

			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6

			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196

		>;

	};



	pinctrl_wdog: wdoggrp {

		fsl,pins = <

			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x166

		>;

	};

};

arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905-2x.dts

0 → 100644
+28 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Copyright 2023 Gateworks Corporation

 */



/dts-v1/;



#include "imx8mp.dtsi"

#include "imx8mp-venice-gw702x.dtsi"

#include "imx8mp-venice-gw7905.dtsi"



/ {

	model = "Gateworks Venice GW7905-2x i.MX8MP Development Kit";

	compatible = "gateworks,imx8mp-gw7905-2x", "fsl,imx8mp";



	chosen {

		stdout-path = &uart2;

	};

};



/* Disable SOM interfaces not used on baseboard */

&eqos {

	status = "disabled";

};



&usdhc1 {

	status = "disabled";

};

arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905.dtsi

0 → 100644
+309 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Copyright 2023 Gateworks Corporation

 */



#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/leds/common.h>

#include <dt-bindings/phy/phy-imx8-pcie.h>



/ {

	led-controller {

		compatible = "gpio-leds";

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_gpio_leds>;



		led-0 {

			function = LED_FUNCTION_STATUS;

			color = <LED_COLOR_ID_GREEN>;

			gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;

			default-state = "on";

			linux,default-trigger = "heartbeat";

		};



		led-1 {

			function = LED_FUNCTION_STATUS;

			color = <LED_COLOR_ID_RED>;

			gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>;

			default-state = "off";

		};

	};



	pcie0_refclk: pcie0-refclk {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <100000000>;

	};



	pps {

		compatible = "pps-gpio";

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_pps>;

		gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;

		status = "okay";

	};



	reg_usb2_vbus: regulator-usb2-vbus {

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_reg_usb2_en>;

		compatible = "regulator-fixed";

		regulator-name = "usb2_vbus";

		gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>;

		enable-active-high;

		regulator-min-microvolt = <5000000>;

		regulator-max-microvolt = <5000000>;

	};



	reg_usdhc2_vmmc: regulator-usdhc2 {

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;

		compatible = "regulator-fixed";

		regulator-name = "SD2_3P3V";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;

		enable-active-high;

	};

};



/* off-board header */

&ecspi2 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_spi2>;

	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;

	status = "okay";

};



&gpio4 {

	gpio-line-names =

		"", "", "", "",

		"", "", "", "",

		"", "", "", "",

		"", "gpioa", "", "",

		"", "", "", "",

		"", "", "", "",

		"", "", "", "",

		"", "", "", "";

};



&gpio4 {

	gpio-line-names =

		"", "gpiod", "", "",

		"gpiob", "gpioc", "", "",

		"", "", "", "",

		"", "", "", "",

		"", "", "", "",

		"", "", "", "",

		"", "", "pci_usb_sel", "",

		"pci_wdis#", "", "", "";

};



&i2c2 {

	clock-frequency = <400000>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_i2c2>;

	status = "okay";



	eeprom@52 {

		compatible = "atmel,24c32";

		reg = <0x52>;

		pagesize = <32>;

	};

};



/* off-board header */

&i2c3 {

	clock-frequency = <400000>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_i2c3>;

	status = "okay";

};



&pcie_phy {

	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;

	fsl,clkreq-unsupported;

	clocks = <&pcie0_refclk>;

	clock-names = "ref";

	status = "okay";

};



&pcie {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_pcie0>;

	reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;

	status = "okay";

};



/* GPS */

&uart1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart1>;

	status = "okay";

};



/* USB1 - Type C front panel SINK port J14 */

&usb3_0 {

	status = "okay";

};



&usb3_phy0 {

	status = "okay";

};



&usb_dwc3_0 {

	dr_mode = "peripheral";

	status = "okay";

};



/* USB2 4-port USB3.0 HUB:

 *  P1 - USBC connector (host only)

 *  P2 - USB2 test connector

 *  P3 - miniPCIe full card

 *  P4 - miniPCIe half card

 */

&usb3_phy1 {

	vbus-supply = <&reg_usb2_vbus>;

	status = "okay";

};



&usb3_1 {

	fsl,permanently-attached;

	fsl,disable-port-power-control;

	status = "okay";

};



&usb_dwc3_1 {

	dr_mode = "host";

	status = "okay";

};



/* microSD */

&usdhc2 {

	pinctrl-names = "default", "state_100mhz", "state_200mhz";

	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;

	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;

	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;

	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;

	vmmc-supply = <&reg_usdhc2_vmmc>;

	bus-width = <4>;

	status = "okay";

};



&iomuxc {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_hog>;



	pinctrl_hog: hoggrp {

		fsl,pins = <

			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13	0x40000040 /* GPIOA */

			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01	0x40000040 /* GPIOD */

			MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04	0x40000040 /* GPIOB */

			MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05	0x40000040 /* GPIOC */

			MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26	0x40000106 /* PCI_USBSEL */

			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28	0x40000106 /* PCI_WDIS# */

		>;

	};



	pinctrl_gpio_leds: gpioledgrp {

		fsl,pins = <

			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22	0x6	/* LEDG */

			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27	0x6	/* LEDR */

		>;

	};



	pinctrl_i2c2: i2c2grp {

		fsl,pins = <

			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2

			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2

		>;

	};



	pinctrl_i2c3: i2c3grp {

		fsl,pins = <

			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2

			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2

		>;

	};



	pinctrl_pcie0: pciegrp {

		fsl,pins = <

			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x106

		>;

	};



	pinctrl_pps: ppsgrp {

		fsl,pins = <

			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21	0x106

		>;

	};



	pinctrl_reg_usb2_en: regusb2grp {

		fsl,pins = <

			MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12	0x6 /* USBHUB_RST# (ext p/u) */

		>;

	};



	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {

		fsl,pins = <

			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40

		>;

	};



	pinctrl_spi2: spi2grp {

		fsl,pins = <

			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK	0x140

			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI	0x140

			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO	0x140

			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13	0x140

		>;

	};



	pinctrl_uart1: uart1grp {

		fsl,pins = <

			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140

			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140

		>;

	};



	pinctrl_usdhc2: usdhc2grp {

		fsl,pins = <

			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190

			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0

			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0

			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0

			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0

			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc0

		>;

	};



	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {

		fsl,pins = <

			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194

			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4

			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4

			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4

			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4

			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc0

		>;

	};



	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {

		fsl,pins = <

			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196

			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6

			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6

			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6

			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6

			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc0

		>;

	};



	pinctrl_usdhc2_gpio: usdhc2gpiogrp {

		fsl,pins = <

			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x1c4

		>;

	};

};