Commit 0d5d3bb6 authored by Namhyung Kim's avatar Namhyung Kim
Browse files

tools headers: Sync arm64 headers with kernel sources 



To pick up changes from:

  b0a3f0e8 ("arm64/sysreg: Replace TCR_EL1 field macros")
  3bbf004c ("arm64: cputype: Add Neoverse-V3AE definitions")
  e185c8a0 ("arm64: cputype: Add NVIDIA Olympus definitions")
  52b49bd6 ("arm64: cputype: Remove duplicate Cortex-X1C definitions")

This should address these tools/perf build warnings:

  Warning: Kernel ABI header differences:
    diff -u tools/arch/arm64/include/asm/cputype.h arch/arm64/include/asm/cputype.h

Please see tools/include/uapi/README.

Note that this is still out of sync due to is_midr_in_range_list().

Reviewed-by: default avatarLeo Yan <leo.yan@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: default avatarNamhyung Kim <namhyung@kernel.org>
parent 369e91bd

tools/arch/arm64/include/asm/cputype.h

+3 −3
Original line number Diff line number Diff line
@@ -81,7 +81,6 @@ 
#define ARM_CPU_PART_CORTEX_A78AE	0xD42

#define ARM_CPU_PART_CORTEX_X1		0xD44

#define ARM_CPU_PART_CORTEX_A510	0xD46

#define ARM_CPU_PART_CORTEX_X1C		0xD4C

#define ARM_CPU_PART_CORTEX_A520	0xD80

#define ARM_CPU_PART_CORTEX_A710	0xD47

#define ARM_CPU_PART_CORTEX_A715	0xD4D
@@ -93,6 +92,7 @@ 
#define ARM_CPU_PART_NEOVERSE_V2	0xD4F

#define ARM_CPU_PART_CORTEX_A720	0xD81

#define ARM_CPU_PART_CORTEX_X4		0xD82

#define ARM_CPU_PART_NEOVERSE_V3AE	0xD83

#define ARM_CPU_PART_NEOVERSE_V3	0xD84

#define ARM_CPU_PART_CORTEX_X925	0xD85

#define ARM_CPU_PART_CORTEX_A725	0xD87
@@ -172,7 +172,6 @@ 
#define MIDR_CORTEX_A78AE	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE)

#define MIDR_CORTEX_X1	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)

#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)

#define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C)

#define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520)

#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)

#define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715)
@@ -184,6 +183,7 @@ 
#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)

#define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720)

#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)

#define MIDR_NEOVERSE_V3AE	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3AE)

#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)

#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)

#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
@@ -247,7 +247,7 @@ 
/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */

#define MIDR_FUJITSU_ERRATUM_010001		MIDR_FUJITSU_A64FX

#define MIDR_FUJITSU_ERRATUM_010001_MASK	(~MIDR_CPU_VAR_REV(1, 0))

#define TCR_CLEAR_FUJITSU_ERRATUM_010001	(TCR_NFD1 | TCR_NFD0)

#define TCR_CLEAR_FUJITSU_ERRATUM_010001	(TCR_EL1_NFD1 | TCR_EL1_NFD0)



#ifndef __ASSEMBLER__