Commit 0d68247e authored by Lucas De Marchi's avatar Lucas De Marchi Committed by Rodrigo Vivi
Browse files

drm/xe/pat: Keep track of relevant indexes 



Some of the PAT entries are relevant for internal driver use, which
varies per platform. Let the PAT early initialization set what they
should point to so the rest of the driver can use them where needed.

Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230927193902.2849159-9-lucas.demarchi@intel.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 45102864

drivers/gpu/drm/xe/xe_device_types.h

+2 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include "xe_devcoredump_types.h"

#include "xe_gt_types.h"

#include "xe_platform_types.h"

#include "xe_pt_types.h"

#include "xe_pmu.h"

#include "xe_step_types.h"
@@ -321,6 +322,7 @@ struct xe_device { 
		const u32 *table;

		/** Number of PAT entries */

		int n_entries;

		u32 idx[__XE_CACHE_LEVEL_COUNT];

	} pat;



	/** @d3cold: Encapsulate d3cold related stuff */

drivers/gpu/drm/xe/xe_pat.c

+12 −0
Original line number Diff line number Diff line
@@ -108,10 +108,16 @@ void xe_pat_init_early(struct xe_device *xe) 
		xe->pat.ops = &xelpg_pat_ops;

		xe->pat.table = xelpg_pat_table;

		xe->pat.n_entries = ARRAY_SIZE(xelpg_pat_table);

		xe->pat.idx[XE_CACHE_NONE] = 2;

		xe->pat.idx[XE_CACHE_WT] = 1;

		xe->pat.idx[XE_CACHE_WB] = 3;

	} else if (xe->info.platform == XE_PVC) {

		xe->pat.ops = &xehp_pat_ops;

		xe->pat.table = xehpc_pat_table;

		xe->pat.n_entries = ARRAY_SIZE(xehpc_pat_table);

		xe->pat.idx[XE_CACHE_NONE] = 0;

		xe->pat.idx[XE_CACHE_WT] = 2;

		xe->pat.idx[XE_CACHE_WB] = 3;

	} else if (xe->info.platform == XE_DG2) {

		/*

		 * Table is the same as previous platforms, but programming
@@ -120,10 +126,16 @@ void xe_pat_init_early(struct xe_device *xe) 
		xe->pat.ops = &xehp_pat_ops;

		xe->pat.table = xelp_pat_table;

		xe->pat.n_entries = ARRAY_SIZE(xelp_pat_table);

		xe->pat.idx[XE_CACHE_NONE] = 3;

		xe->pat.idx[XE_CACHE_WT] = 2;

		xe->pat.idx[XE_CACHE_WB] = 0;

	} else if (GRAPHICS_VERx100(xe) <= 1210) {

		xe->pat.ops = &xelp_pat_ops;

		xe->pat.table = xelp_pat_table;

		xe->pat.n_entries = ARRAY_SIZE(xelp_pat_table);

		xe->pat.idx[XE_CACHE_NONE] = 3;

		xe->pat.idx[XE_CACHE_WT] = 2;

		xe->pat.idx[XE_CACHE_WB] = 0;

	} else {

		/*

		 * Going forward we expect to need new PAT settings for most

drivers/gpu/drm/xe/xe_pt_types.h

+1 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ enum xe_cache_level { 
	XE_CACHE_NONE,

	XE_CACHE_WT,

	XE_CACHE_WB,

	__XE_CACHE_LEVEL_COUNT,

};



#define XE_VM_MAX_LEVEL 4