Commit 0d80bbe2 authored by Sergey Temerkhanov's avatar Sergey Temerkhanov Committed by Jakub Kicinski
Browse files

ice: Implement Tx interrupt enablement functions 



Introduce functions enabling/disabling Tx TS interrupts
for the E822 and ETH56G PHYs

Signed-off-by: default avatarSergey Temerkhanov <sergey.temerkhanov@intel.com>
Reviewed-by: default avatarPrzemek Kitszel <przemyslaw.kitszel@intel.com>
Reviewed-by: default avatarArkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Signed-off-by: default avatarKarol Kolacinski <karol.kolacinski@intel.com>
Tested-by: default avatarPucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com>
Signed-off-by: default avatarJacob Keller <jacob.e.keller@intel.com>
Link: https://lore.kernel.org/r/20240528-next-2024-05-28-ptp-refactors-v1-3-c082739bb6f6@intel.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 579a2302

drivers/net/ethernet/intel/ice/ice_ptp.c

+34 −32
Original line number Diff line number Diff line
@@ -1457,42 +1457,46 @@ void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup) 
 * @ena: bool value to enable or disable interrupt

 * @threshold: Minimum number of packets at which intr is triggered

 *

 * Utility function to enable or disable Tx timestamp interrupt and threshold

 * Utility function to configure all the PHY interrupt settings, including

 * whether the PHY interrupt is enabled, and what threshold to use. Also

 * configures The E82X timestamp owner to react to interrupts from all PHYs.

 *

 * Return: 0 on success, -EOPNOTSUPP when PHY model incorrect, other error codes

 * when failed to configure PHY interrupt for E82X

 */

static int ice_ptp_cfg_phy_interrupt(struct ice_pf *pf, bool ena, u32 threshold)

{

	struct device *dev = ice_pf_to_dev(pf);

	struct ice_hw *hw = &pf->hw;

	int err = 0;

	int quad;

	u32 val;



	ice_ptp_reset_ts_memory(hw);



	for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++) {

		err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG,

					     &val);

		if (err)

			break;

	switch (hw->ptp.phy_model) {

	case ICE_PHY_E82X: {

		int quad;



		if (ena) {

			val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;

			val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;

			val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M,

					  threshold);

		} else {

			val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;

		}

		for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports);

		     quad++) {

			int err;



		err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG,

					      val);

		if (err)

			break;

			err = ice_phy_cfg_intr_e82x(hw, quad, ena, threshold);

			if (err) {

				dev_err(dev, "Failed to configure PHY interrupt for quad %d, err %d\n",

					quad, err);

				return err;

			}

		}



	if (err)

		dev_err(ice_pf_to_dev(pf), "PTP failed in intr ena, err %d\n",

			err);

	return err;

		return 0;

	}

	case ICE_PHY_E810:

		return 0;

	case ICE_PHY_UNSUP:

	default:

		dev_warn(dev, "%s: Unexpected PHY model %d\n", __func__,

			 hw->ptp.phy_model);

		return -EOPNOTSUPP;

	}

}



/**
@@ -3010,12 +3014,10 @@ static int ice_ptp_init_owner(struct ice_pf *pf) 
	/* Release the global hardware lock */

	ice_ptp_unlock(hw);



	if (!ice_is_e810(hw)) {

		/* Enable quad interrupts */

	/* Configure PHY interrupt settings */

	err = ice_ptp_cfg_phy_interrupt(pf, true, 1);

	if (err)

		goto err_exit;

	}



	/* Ensure we have a clock device */

	err = ice_ptp_create_clock(pf);

drivers/net/ethernet/intel/ice/ice_ptp_hw.c

+31 −0
Original line number Diff line number Diff line
@@ -2719,6 +2719,37 @@ ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8 quad, u64 *tstamp_ready) 
	return 0;

}



/**

 * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt

 * @hw: pointer to the HW struct

 * @quad: the timestamp quad

 * @ena: enable or disable interrupt

 * @threshold: interrupt threshold

 *

 * Configure TX timestamp interrupt for the specified quad

 *

 * Return: 0 on success, other error codes when failed to read/write quad

 */



int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold)

{

	int err;

	u32 val;



	err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val);

	if (err)

		return err;



	val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;

	if (ena) {

		val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;

		val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;

		val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M, threshold);

	}



	return ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val);

}



/**

 * ice_ptp_init_phy_e82x - initialize PHY parameters

 * @ptp: pointer to the PTP HW struct

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

+1 −3
Original line number Diff line number Diff line
@@ -265,6 +265,7 @@ int ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset); 
int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port);

int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port);

int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port);

int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold);



/* E810 family functions */

int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);
@@ -342,11 +343,8 @@ int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id, 
#define Q_REG_TX_MEM_GBL_CFG		0xC08

#define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S	0

#define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M	BIT(0)

#define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_S	1

#define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M	ICE_M(0xFF, 1)

#define Q_REG_TX_MEM_GBL_CFG_INTR_THR_S	9

#define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M ICE_M(0x3F, 9)

#define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_S	15

#define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M	BIT(15)



/* Tx Timestamp data registers */