Commit 0d988e5d authored by George Shen's avatar George Shen Committed by Alex Deucher
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drm/amd/display: Remove CR AUX RD Interval limit for LTTPR 



[Why]
DP spec specifies that DPRX shall use the read interval in the
TRAINING_AUX_RD_INTERVAL_PHY_REPEATER LTTPR DPCD register. This
register's bit definition is the same as the AUX read interval register
for DPRX.

[How}
Remove logic which forces AUX read interval to 100us for repeaters when
in LTTPR non-transparent mode.

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarWesley Chalmers <wesley.chalmers@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarGeorge Shen <George.Shen@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3db817fc

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+0 −3
Original line number Diff line number Diff line
@@ -1544,9 +1544,6 @@ static enum link_training_result perform_clock_recovery_sequence( 
		/* 3. wait receiver to lock-on*/

		wait_time_microsec = lt_settings->cr_pattern_time;



		if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)

			wait_time_microsec = TRAINING_AUX_RD_INTERVAL;



		if (link->dc->debug.apply_vendor_specific_lttpr_wa &&

				(link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN)) {

			wait_time_microsec = 16000;