Commit 0dc11618 authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Stephen Boyd
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clk: mediatek: mt8188-vdo1: Add VDO1_DPI1_HDMI clock for hdmitx 



Add a missing clock found in the VDO1 controller for the HDMI TX
controller over DPI1.

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250212100342.33618-2-angelogioacchino.delregno@collabora.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 8c1d4d8f

drivers/clk/mediatek/clk-mt8188-vdo1.c

+11 −0
Original line number Diff line number Diff line
@@ -43,6 +43,12 @@ static const struct mtk_gate_regs vdo1_4_cg_regs = { 
	.sta_ofs = 0x140,

};



static const struct mtk_gate_regs vdo1_5_cg_regs = {

	.set_ofs = 0x400,

	.clr_ofs = 0x400,

	.sta_ofs = 0x400,

};



#define GATE_VDO1_0(_id, _name, _parent, _shift)			\

	GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
@@ -62,6 +68,9 @@ static const struct mtk_gate_regs vdo1_4_cg_regs = { 
#define GATE_VDO1_4(_id, _name, _parent, _shift)			\

	GATE_MTK(_id, _name, _parent, &vdo1_4_cg_regs, _shift, &mtk_clk_gate_ops_setclr)



#define GATE_VDO1_5(_id, _name, _parent, _shift)			\

	GATE_MTK(_id, _name, _parent, &vdo1_5_cg_regs, _shift, &mtk_clk_gate_ops_setclr)



static const struct mtk_gate vdo1_clks[] = {

	/* VDO1_0 */

	GATE_VDO1_0(CLK_VDO1_SMI_LARB2, "vdo1_smi_larb2", "top_vpp", 0),
@@ -129,6 +138,8 @@ static const struct mtk_gate vdo1_clks[] = { 
	GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf_ck", "top_vpp", 17),

	/* VDO1_4 */

	GATE_VDO1_4(CLK_VDO1_26M_SLOW, "vdo1_26m_slow_ck", "clk26m", 8),

	/* VDO1_5 */

	GATE_VDO1_5(CLK_VDO1_DPI1_HDMI, "vdo1_dpi1_hdmi", "hdmi_txpll", 0),

};



static const struct mtk_clk_desc vdo1_desc = {