Commit 0dd21f83 authored by Jouni Högander's avatar Jouni Högander
Browse files

drm/i915/psr: Silence period and lfps half cycle 



Add get function for silence period and lfps half cycle. Values are taken
from the tables in bspec.

Bspec: 71632

v3:
  - use PORT_ALPM_CTL_SILENCE_PERIOD_MASK instead of value 255
  - use PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK instead of
    value 31
v2:
  - fix some checks
  - add some more comments

Signed-off-by: default avatarJouni Högander <jouni.hogander@intel.com>
Reviewed-by: default avatarAnimesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240328141928.1311284-4-jouni.hogander@intel.com
parent da6a9836

drivers/gpu/drm/i915/display/intel_display_types.h

+2 −0
Original line number Diff line number Diff line
@@ -1746,6 +1746,8 @@ struct intel_psr { 


		/* LNL and beyond */

		u8 check_entry_lines;

		u8 silence_period_sym_clocks;

		u8 lfps_half_cycle_num_of_syms;

	} alpm_parameters;



	ktime_t last_entry_attempt;

drivers/gpu/drm/i915/display/intel_psr.c

+80 −2
Original line number Diff line number Diff line
@@ -1126,6 +1126,74 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d 
	return true;

}



/*

 * See Bspec: 71632 for the table

 *

 * Silence_period = tSilence,Min + ((tSilence,Max - tSilence,Min) / 2)

 *

 * Half cycle duration:

 *

 * Link rates 1.62 - 4.32 and tLFPS_Cycle = 70 ns

 * FLOOR( (Link Rate * tLFPS_Cycle) / (2 * 10) )

 *

 * Link rates 5.4 - 8.1

 * PORT_ALPM_LFPS_CTL[ LFPS Cycle Count ] = 10

 * LFPS Period chosen is the mid-point of the min:max values from the table

 * FLOOR( LFPS Period in Symbol clocks /

 * (2 * PORT_ALPM_LFPS_CTL[ LFPS Cycle Count ]) )

 */

static bool _lnl_get_silence_period_and_lfps_half_cycle(int link_rate,

							int *silence_period,

							int *lfps_half_cycle)

{

	switch (link_rate) {

	case 162000:

		*silence_period = 20;

		*lfps_half_cycle = 5;

		break;

	case 216000:

		*silence_period = 27;

		*lfps_half_cycle = 7;

		break;

	case 243000:

		*silence_period = 31;

		*lfps_half_cycle = 8;

		break;

	case 270000:

		*silence_period = 34;

		*lfps_half_cycle = 9;

		break;

	case 324000:

		*silence_period = 41;

		*lfps_half_cycle = 11;

		break;

	case 432000:

		*silence_period = 56;

		*lfps_half_cycle = 15;

		break;

	case 540000:

		*silence_period = 69;

		*lfps_half_cycle = 12;

		break;

	case 648000:

		*silence_period = 84;

		*lfps_half_cycle = 15;

		break;

	case 675000:

		*silence_period = 87;

		*lfps_half_cycle = 15;

		break;

	case 810000:

		*silence_period = 104;

		*lfps_half_cycle = 19;

		break;

	default:

		*silence_period = *lfps_half_cycle = -1;

		return false;

	}

	return true;

}



/*

 * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+

 * tSilence, Max+ tPHY Establishment + tCDS) / tline)
@@ -1165,20 +1233,30 @@ static int _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp, 
					     struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *i915 = dp_to_i915(intel_dp);

	int aux_less_wake_time, aux_less_wake_lines;

	int aux_less_wake_time, aux_less_wake_lines, silence_period,

		lfps_half_cycle;



	aux_less_wake_time =

		_lnl_compute_aux_less_wake_time(crtc_state->port_clock);

	aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,

						       aux_less_wake_time);



	if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK)

	if (!_lnl_get_silence_period_and_lfps_half_cycle(intel_dp->link_rate,

							 &silence_period,

							 &lfps_half_cycle))

		return false;



	if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK ||

	    silence_period > PORT_ALPM_CTL_SILENCE_PERIOD_MASK ||

	    lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK)

		return false;



	if (i915->display.params.psr_safest_params)

		aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK;



	intel_dp->psr.alpm_parameters.fast_wake_lines = aux_less_wake_lines;

	intel_dp->psr.alpm_parameters.silence_period_sym_clocks = silence_period;

	intel_dp->psr.alpm_parameters.lfps_half_cycle_num_of_syms = lfps_half_cycle;



	return true;

}