Commit 0dd2dd01 authored by Maarten Lankhorst's avatar Maarten Lankhorst Committed by Lucas De Marchi
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drm/xe: Move DSB l2 flush to a more sensible place 



Flushing l2 is only needed after all data has been written.

Fixes: 01570b44 ("drm/xe/bmg: implement Wa_16023588340")
Signed-off-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: stable@vger.kernel.org # v6.12+
Reviewed-by: default avatarMatthew Auld <matthew.auld@intel.com>
Signed-off-by: default avatarMatthew Auld <matthew.auld@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/20250606104546.1996818-3-matthew.auld@intel.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent deea6a7d

drivers/gpu/drm/xe/display/xe_dsb_buffer.c

+4 −7
Original line number Diff line number Diff line
@@ -17,10 +17,7 @@ u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf) 


void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val)

{

	struct xe_device *xe = dsb_buf->vma->bo->tile->xe;



	iosys_map_wr(&dsb_buf->vma->bo->vmap, idx * 4, u32, val);

	xe_device_l2_flush(xe);

}



u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
@@ -30,12 +27,9 @@ u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx) 


void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size)

{

	struct xe_device *xe = dsb_buf->vma->bo->tile->xe;



	WARN_ON(idx > (dsb_buf->buf_size - size) / sizeof(*dsb_buf->cmd_buf));



	iosys_map_memset(&dsb_buf->vma->bo->vmap, idx * 4, val, size);

	xe_device_l2_flush(xe);

}



bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *dsb_buf, size_t size)
@@ -74,9 +68,12 @@ void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf) 


void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)

{

	struct xe_device *xe = dsb_buf->vma->bo->tile->xe;



	/*

	 * The memory barrier here is to ensure coherency of DSB vs MMIO,

	 * both for weak ordering archs and discrete cards.

	 */

	xe_device_wmb(dsb_buf->vma->bo->tile->xe);

	xe_device_wmb(xe);

	xe_device_l2_flush(xe);

}