Commit 0dffea1e authored by Anusha Srivatsa's avatar Anusha Srivatsa Committed by Radhakrishna Sripada
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drm/i915/xe2hpd: Configure CHICKEN_MISC_2 before enabling planes 



Add step 9 from initialize display sequence.

v2: Commit subject improved

Bpsec: 49189
Signed-off-by: default avatarAnusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: default avatarBalasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-11-radhakrishna.sripada@intel.com
parent 2de02cb1

drivers/gpu/drm/i915/display/intel_display_power.c

+4 −0
Original line number Diff line number Diff line
@@ -1688,6 +1688,10 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, 
	if (IS_DG2(dev_priv))

		intel_snps_phy_wait_for_calibration(dev_priv);



	/* 9. XE2_HPD: Program CHICKEN_MISC_2 before any cursor or planes are enabled */

	if (DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 1))

		intel_de_rmw(dev_priv, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1);



	if (resume)

		intel_dmc_load_program(dev_priv);

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -3449,6 +3449,7 @@ 


#define CHICKEN_MISC_2		_MMIO(0x42084)

#define   CHICKEN_MISC_DISABLE_DPT	REG_BIT(30) /* adl,dg2 */

#define   BMG_DARB_HALF_BLK_END_BURST	REG_BIT(27)

#define   KBL_ARB_FILL_SPARE_14		REG_BIT(14)

#define   KBL_ARB_FILL_SPARE_13		REG_BIT(13)

#define   GLK_CL2_PWR_DOWN		REG_BIT(12)