Commit 0e2fa91c authored by Russell King (Oracle)'s avatar Russell King (Oracle) Committed by Jakub Kicinski
Browse files

net: stmmac: ingenic: use stmmac_get_phy_intf_sel() 



Use stmmac_get_phy_intf_sel() to decode the PHY interface mode to the
phy_intf_sel value, validate the result against the SoC specific
supported phy_intf_sel values, and pass into the SoC specific
set_mode() methods, replacing the local phy_intf_sel variable. This
provides the value for the MACPHYC_PHY_INFT_MASK field.

Reviewed-by: default avatarMaxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1vHHq8-0000000DjrJ-2NRK@rmk-PC.armlinux.org.uk


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 14497aaa

drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c

+34 −21
Original line number Diff line number Diff line
@@ -64,28 +64,27 @@ struct ingenic_soc_info { 
	enum ingenic_mac_version version;

	u32 mask;



	int (*set_mode)(struct plat_stmmacenet_data *plat_dat);

	int (*set_mode)(struct plat_stmmacenet_data *plat_dat, u8 phy_intf_sel);



	u8 valid_phy_intf_sel;

};



static int jz4775_mac_set_mode(struct plat_stmmacenet_data *plat_dat)

static int jz4775_mac_set_mode(struct plat_stmmacenet_data *plat_dat,

			       u8 phy_intf_sel)

{

	struct ingenic_mac *mac = plat_dat->bsp_priv;

	unsigned int val;

	u8 phy_intf_sel;



	switch (plat_dat->phy_interface) {

	case PHY_INTERFACE_MODE_MII:

		phy_intf_sel = PHY_INTF_SEL_GMII_MII;

		dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_MII\n");

		break;



	case PHY_INTERFACE_MODE_GMII:

		phy_intf_sel = PHY_INTF_SEL_GMII_MII;

		dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_GMII\n");

		break;



	case PHY_INTERFACE_MODE_RMII:

		phy_intf_sel = PHY_INTF_SEL_RMII;

		dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");

		break;
@@ -93,7 +92,6 @@ static int jz4775_mac_set_mode(struct plat_stmmacenet_data *plat_dat) 
	case PHY_INTERFACE_MODE_RGMII_ID:

	case PHY_INTERFACE_MODE_RGMII_TXID:

	case PHY_INTERFACE_MODE_RGMII_RXID:

		phy_intf_sel = PHY_INTF_SEL_RGMII;

		dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RGMII\n");

		break;
@@ -110,7 +108,8 @@ static int jz4775_mac_set_mode(struct plat_stmmacenet_data *plat_dat) 
	return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);

}



static int x1000_mac_set_mode(struct plat_stmmacenet_data *plat_dat)

static int x1000_mac_set_mode(struct plat_stmmacenet_data *plat_dat,

			      u8 phy_intf_sel)

{

	struct ingenic_mac *mac = plat_dat->bsp_priv;
@@ -129,15 +128,14 @@ static int x1000_mac_set_mode(struct plat_stmmacenet_data *plat_dat) 
	return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, 0);

}



static int x1600_mac_set_mode(struct plat_stmmacenet_data *plat_dat)

static int x1600_mac_set_mode(struct plat_stmmacenet_data *plat_dat,

			      u8 phy_intf_sel)

{

	struct ingenic_mac *mac = plat_dat->bsp_priv;

	unsigned int val;

	u8 phy_intf_sel;



	switch (plat_dat->phy_interface) {

	case PHY_INTERFACE_MODE_RMII:

		phy_intf_sel = PHY_INTF_SEL_RMII;

		dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");

		break;
@@ -153,16 +151,15 @@ static int x1600_mac_set_mode(struct plat_stmmacenet_data *plat_dat) 
	return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);

}



static int x1830_mac_set_mode(struct plat_stmmacenet_data *plat_dat)

static int x1830_mac_set_mode(struct plat_stmmacenet_data *plat_dat,

			      u8 phy_intf_sel)

{

	struct ingenic_mac *mac = plat_dat->bsp_priv;

	unsigned int val;

	u8 phy_intf_sel;



	switch (plat_dat->phy_interface) {

	case PHY_INTERFACE_MODE_RMII:

		val = FIELD_PREP(MACPHYC_MODE_SEL_MASK, MACPHYC_MODE_SEL_RMII);

		phy_intf_sel = PHY_INTF_SEL_RMII;

		dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");

		break;
@@ -178,17 +175,16 @@ static int x1830_mac_set_mode(struct plat_stmmacenet_data *plat_dat) 
	return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);

}



static int x2000_mac_set_mode(struct plat_stmmacenet_data *plat_dat)

static int x2000_mac_set_mode(struct plat_stmmacenet_data *plat_dat,

			      u8 phy_intf_sel)

{

	struct ingenic_mac *mac = plat_dat->bsp_priv;

	unsigned int val;

	u8 phy_intf_sel;



	switch (plat_dat->phy_interface) {

	case PHY_INTERFACE_MODE_RMII:

		val = FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN) |

			  FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN);

		phy_intf_sel = PHY_INTF_SEL_RMII;

		dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");

		break;
@@ -197,8 +193,6 @@ static int x2000_mac_set_mode(struct plat_stmmacenet_data *plat_dat) 
	case PHY_INTERFACE_MODE_RGMII_TXID:

	case PHY_INTERFACE_MODE_RGMII_RXID:

		val = 0;

		phy_intf_sel = PHY_INTF_SEL_RGMII;



		if (mac->tx_delay == 0)

			val |= FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN);

		else
@@ -229,10 +223,21 @@ static int x2000_mac_set_mode(struct plat_stmmacenet_data *plat_dat) 
static int ingenic_mac_init(struct platform_device *pdev, void *bsp_priv)

{

	struct ingenic_mac *mac = bsp_priv;

	int ret;

	phy_interface_t interface;

	int phy_intf_sel, ret;



	if (mac->soc_info->set_mode) {

		ret = mac->soc_info->set_mode(mac->plat_dat);

		interface = mac->plat_dat->phy_interface;



		phy_intf_sel = stmmac_get_phy_intf_sel(interface);

		if (phy_intf_sel < 0 || phy_intf_sel >= BITS_PER_BYTE ||

		    ~mac->soc_info->valid_phy_intf_sel & BIT(phy_intf_sel)) {

			dev_err(mac->dev, "unsupported interface %s\n",

				phy_modes(interface));

			return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL;

		}



		ret = mac->soc_info->set_mode(mac->plat_dat, phy_intf_sel);

		if (ret)

			return ret;

	}
@@ -309,6 +314,9 @@ static struct ingenic_soc_info jz4775_soc_info = { 
	.mask = MACPHYC_TXCLK_SEL_MASK | MACPHYC_SOFT_RST_MASK | MACPHYC_PHY_INFT_MASK,



	.set_mode = jz4775_mac_set_mode,

	.valid_phy_intf_sel = BIT(PHY_INTF_SEL_GMII_MII) |

			      BIT(PHY_INTF_SEL_RGMII) |

			      BIT(PHY_INTF_SEL_RMII),

};



static struct ingenic_soc_info x1000_soc_info = {
@@ -316,6 +324,7 @@ static struct ingenic_soc_info x1000_soc_info = { 
	.mask = MACPHYC_SOFT_RST_MASK,



	.set_mode = x1000_mac_set_mode,

	.valid_phy_intf_sel = BIT(PHY_INTF_SEL_RMII),

};



static struct ingenic_soc_info x1600_soc_info = {
@@ -323,6 +332,7 @@ static struct ingenic_soc_info x1600_soc_info = { 
	.mask = MACPHYC_SOFT_RST_MASK | MACPHYC_PHY_INFT_MASK,



	.set_mode = x1600_mac_set_mode,

	.valid_phy_intf_sel = BIT(PHY_INTF_SEL_RMII),

};



static struct ingenic_soc_info x1830_soc_info = {
@@ -330,6 +340,7 @@ static struct ingenic_soc_info x1830_soc_info = { 
	.mask = MACPHYC_MODE_SEL_MASK | MACPHYC_SOFT_RST_MASK | MACPHYC_PHY_INFT_MASK,



	.set_mode = x1830_mac_set_mode,

	.valid_phy_intf_sel = BIT(PHY_INTF_SEL_RMII),

};



static struct ingenic_soc_info x2000_soc_info = {
@@ -338,6 +349,8 @@ static struct ingenic_soc_info x2000_soc_info = { 
			MACPHYC_RX_DELAY_MASK | MACPHYC_SOFT_RST_MASK | MACPHYC_PHY_INFT_MASK,



	.set_mode = x2000_mac_set_mode,

	.valid_phy_intf_sel = BIT(PHY_INTF_SEL_RGMII) |

			      BIT(PHY_INTF_SEL_RMII),

};



static const struct of_device_id ingenic_mac_of_matches[] = {