Commit 0e37e4b9 authored Sep 14, 2024 by Fudongwang Committed by Alex Deucher Oct 07, 2024

drm/amd/display: skip disable CRTC in seemless bootup case



Resync FIFO is a workaround to write the same value to
DENTIST_DISPCLK_CNTL register after programming OTG_PIXEL_RATE_DIV
register, in case seemless boot, there is no OTG_PIXEL_RATE_DIV register
update, so skip CRTC disable when resync FIFO to avoid random FIFO error
and garbage.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Fudongwang <Fudong.Wang@amd.com>
Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 8cb028a1

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -371,7 +371,9 @@ void dcn314_resync_fifo_dccg_dio(struct dce_hwseq hws, struct dc dc, struct dc
		if (pipe->top_pipe \|\| pipe->prev_odm_pipe)
		continue;

		if (pipe->stream && (pipe->stream->dpms_off \|\| dc_is_virtual_signal(pipe->stream->signal))) {
		if (pipe->stream && (pipe->stream->dpms_off \|\| dc_is_virtual_signal(pipe->stream->signal)) &&
		!pipe->stream->apply_seamless_boot_optimization &&
		!pipe->stream->apply_edp_fast_boot_optimization) {
		pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);
		reset_sync_context_for_pipe(dc, context, i);
		otg_disabled[i] = true;