Commit 0e3f7d12 authored by Nuno Das Neves's avatar Nuno Das Neves Committed by Wei Liu
Browse files

hyperv-tlfs: Change prefix of generic HV_REGISTER_* MSRs to HV_MSR_* 



The HV_REGISTER_ are used as arguments to hv_set/get_register(), which
delegate to arch-specific mechanisms for getting/setting synthetic
Hyper-V MSRs.

On arm64, HV_REGISTER_ defines are synthetic VP registers accessed via
the get/set vp registers hypercalls. The naming matches the TLFS
document, although these register names are not specific to arm64.

However, on x86 the prefix HV_REGISTER_ indicates Hyper-V MSRs accessed
via rdmsrl()/wrmsrl(). This is not consistent with the TLFS doc, where
HV_REGISTER_ is *only* used for used for VP register names used by
the get/set register hypercalls.

To fix this inconsistency and prevent future confusion, change the
arch-generic aliases used by callers of hv_set/get_register() to have
the prefix HV_MSR_ instead of HV_REGISTER_.

Use the prefix HV_X64_MSR_ for the x86-only Hyper-V MSRs. On x86, the
generic HV_MSR_'s point to the corresponding HV_X64_MSR_.

Move the arm64 HV_REGISTER_* defines to the asm-generic hyperv-tlfs.h,
since these are not specific to arm64. On arm64, the generic HV_MSR_'s
point to the corresponding HV_REGISTER_.

While at it, rename hv_get/set_registers() and related functions to
hv_get/set_msr(), hv_get/set_nested_msr(), etc. These are only used for
Hyper-V MSRs and this naming makes that clear.

Signed-off-by: default avatarNuno Das Neves <nunodasneves@linux.microsoft.com>
Reviewed-by: default avatarWei Liu <wei.liu@kernel.org>
Reviewed-by: default avatarMichael Kelley <mhklinux@outlook.com>
Link: https://lore.kernel.org/r/1708440933-27125-1-git-send-email-nunodasneves@linux.microsoft.com


Signed-off-by: default avatarWei Liu <wei.liu@kernel.org>
Message-ID: <1708440933-27125-1-git-send-email-nunodasneves@linux.microsoft.com>
parent d206a76d

arch/arm64/include/asm/hyperv-tlfs.h

+19 −26
Original line number Diff line number Diff line
@@ -21,14 +21,6 @@ 
 * byte ordering of Linux running on ARM64, so no special handling is required.

 */



/*

 * These Hyper-V registers provide information equivalent to the CPUID

 * instruction on x86/x64.

 */

#define HV_REGISTER_HYPERVISOR_VERSION		0x00000100 /*CPUID 0x40000002 */

#define HV_REGISTER_FEATURES			0x00000200 /*CPUID 0x40000003 */

#define HV_REGISTER_ENLIGHTENMENTS		0x00000201 /*CPUID 0x40000004 */



/*

 * Group C Features. See the asm-generic version of hyperv-tlfs.h

 * for a description of Feature Groups.
@@ -41,28 +33,29 @@ 
#define HV_STIMER_DIRECT_MODE_AVAILABLE		BIT(13)



/*

 * Synthetic register definitions equivalent to MSRs on x86/x64

 * To support arch-generic code calling hv_set/get_register:

 * - On x86, HV_MSR_ indicates an MSR accessed via rdmsrl/wrmsrl

 * - On ARM, HV_MSR_ indicates a VP register accessed via hypercall

 */

#define HV_REGISTER_CRASH_P0		0x00000210

#define HV_REGISTER_CRASH_P1		0x00000211

#define HV_REGISTER_CRASH_P2		0x00000212

#define HV_REGISTER_CRASH_P3		0x00000213

#define HV_REGISTER_CRASH_P4		0x00000214

#define HV_REGISTER_CRASH_CTL		0x00000215

#define HV_MSR_CRASH_P0		(HV_REGISTER_CRASH_P0)

#define HV_MSR_CRASH_P1		(HV_REGISTER_CRASH_P1)

#define HV_MSR_CRASH_P2		(HV_REGISTER_CRASH_P2)

#define HV_MSR_CRASH_P3		(HV_REGISTER_CRASH_P3)

#define HV_MSR_CRASH_P4		(HV_REGISTER_CRASH_P4)

#define HV_MSR_CRASH_CTL	(HV_REGISTER_CRASH_CTL)



#define HV_REGISTER_GUEST_OSID		0x00090002

#define HV_REGISTER_VP_INDEX		0x00090003

#define HV_REGISTER_TIME_REF_COUNT	0x00090004

#define HV_REGISTER_REFERENCE_TSC	0x00090017

#define HV_MSR_VP_INDEX		(HV_REGISTER_VP_INDEX)

#define HV_MSR_TIME_REF_COUNT	(HV_REGISTER_TIME_REF_COUNT)

#define HV_MSR_REFERENCE_TSC	(HV_REGISTER_REFERENCE_TSC)



#define HV_REGISTER_SINT0		0x000A0000

#define HV_REGISTER_SCONTROL		0x000A0010

#define HV_REGISTER_SIEFP		0x000A0012

#define HV_REGISTER_SIMP		0x000A0013

#define HV_REGISTER_EOM			0x000A0014

#define HV_MSR_SINT0		(HV_REGISTER_SINT0)

#define HV_MSR_SCONTROL		(HV_REGISTER_SCONTROL)

#define HV_MSR_SIEFP		(HV_REGISTER_SIEFP)

#define HV_MSR_SIMP		(HV_REGISTER_SIMP)

#define HV_MSR_EOM		(HV_REGISTER_EOM)



#define HV_REGISTER_STIMER0_CONFIG	0x000B0000

#define HV_REGISTER_STIMER0_COUNT	0x000B0001

#define HV_MSR_STIMER0_CONFIG	(HV_REGISTER_STIMER0_CONFIG)

#define HV_MSR_STIMER0_COUNT	(HV_REGISTER_STIMER0_COUNT)



union hv_msi_entry {

	u64 as_uint64[2];

arch/arm64/include/asm/mshyperv.h

+2 −2
Original line number Diff line number Diff line
@@ -31,12 +31,12 @@ void hv_set_vpreg(u32 reg, u64 value); 
u64 hv_get_vpreg(u32 reg);

void hv_get_vpreg_128(u32 reg, struct hv_get_vp_registers_output *result);



static inline void hv_set_register(unsigned int reg, u64 value)

static inline void hv_set_msr(unsigned int reg, u64 value)

{

	hv_set_vpreg(reg, value);

}



static inline u64 hv_get_register(unsigned int reg)

static inline u64 hv_get_msr(unsigned int reg)

{

	return hv_get_vpreg(reg);

}

arch/x86/hyperv/hv_init.c

+4 −4
Original line number Diff line number Diff line
@@ -667,14 +667,14 @@ void hyperv_cleanup(void) 
	hv_hypercall_pg = NULL;



	/* Reset the hypercall page */

	hypercall_msr.as_uint64 = hv_get_register(HV_X64_MSR_HYPERCALL);

	hypercall_msr.as_uint64 = hv_get_msr(HV_X64_MSR_HYPERCALL);

	hypercall_msr.enable = 0;

	hv_set_register(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);

	hv_set_msr(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);



	/* Reset the TSC page */

	tsc_msr.as_uint64 = hv_get_register(HV_X64_MSR_REFERENCE_TSC);

	tsc_msr.as_uint64 = hv_get_msr(HV_X64_MSR_REFERENCE_TSC);

	tsc_msr.enable = 0;

	hv_set_register(HV_X64_MSR_REFERENCE_TSC, tsc_msr.as_uint64);

	hv_set_msr(HV_X64_MSR_REFERENCE_TSC, tsc_msr.as_uint64);

}



void hyperv_report_panic(struct pt_regs *regs, long err, bool in_die)

arch/x86/include/asm/hyperv-tlfs.h

+76 −69
Original line number Diff line number Diff line
@@ -182,7 +182,7 @@ enum hv_isolation_type { 
#define HV_X64_MSR_HYPERCALL			0x40000001



/* MSR used to provide vcpu index */

#define HV_REGISTER_VP_INDEX			0x40000002

#define HV_X64_MSR_VP_INDEX			0x40000002



/* MSR used to reset the guest OS. */

#define HV_X64_MSR_RESET			0x40000003
@@ -191,10 +191,10 @@ enum hv_isolation_type { 
#define HV_X64_MSR_VP_RUNTIME			0x40000010



/* MSR used to read the per-partition time reference counter */

#define HV_REGISTER_TIME_REF_COUNT		0x40000020

#define HV_X64_MSR_TIME_REF_COUNT		0x40000020



/* A partition's reference time stamp counter (TSC) page */

#define HV_REGISTER_REFERENCE_TSC		0x40000021

#define HV_X64_MSR_REFERENCE_TSC		0x40000021



/* MSR used to retrieve the TSC frequency */

#define HV_X64_MSR_TSC_FREQUENCY		0x40000022
@@ -209,61 +209,61 @@ enum hv_isolation_type { 
#define HV_X64_MSR_VP_ASSIST_PAGE		0x40000073



/* Define synthetic interrupt controller model specific registers. */

#define HV_REGISTER_SCONTROL			0x40000080

#define HV_REGISTER_SVERSION			0x40000081

#define HV_REGISTER_SIEFP			0x40000082

#define HV_REGISTER_SIMP			0x40000083

#define HV_REGISTER_EOM				0x40000084

#define HV_REGISTER_SINT0			0x40000090

#define HV_REGISTER_SINT1			0x40000091

#define HV_REGISTER_SINT2			0x40000092

#define HV_REGISTER_SINT3			0x40000093

#define HV_REGISTER_SINT4			0x40000094

#define HV_REGISTER_SINT5			0x40000095

#define HV_REGISTER_SINT6			0x40000096

#define HV_REGISTER_SINT7			0x40000097

#define HV_REGISTER_SINT8			0x40000098

#define HV_REGISTER_SINT9			0x40000099

#define HV_REGISTER_SINT10			0x4000009A

#define HV_REGISTER_SINT11			0x4000009B

#define HV_REGISTER_SINT12			0x4000009C

#define HV_REGISTER_SINT13			0x4000009D

#define HV_REGISTER_SINT14			0x4000009E

#define HV_REGISTER_SINT15			0x4000009F

#define HV_X64_MSR_SCONTROL			0x40000080

#define HV_X64_MSR_SVERSION			0x40000081

#define HV_X64_MSR_SIEFP			0x40000082

#define HV_X64_MSR_SIMP				0x40000083

#define HV_X64_MSR_EOM				0x40000084

#define HV_X64_MSR_SINT0			0x40000090

#define HV_X64_MSR_SINT1			0x40000091

#define HV_X64_MSR_SINT2			0x40000092

#define HV_X64_MSR_SINT3			0x40000093

#define HV_X64_MSR_SINT4			0x40000094

#define HV_X64_MSR_SINT5			0x40000095

#define HV_X64_MSR_SINT6			0x40000096

#define HV_X64_MSR_SINT7			0x40000097

#define HV_X64_MSR_SINT8			0x40000098

#define HV_X64_MSR_SINT9			0x40000099

#define HV_X64_MSR_SINT10			0x4000009A

#define HV_X64_MSR_SINT11			0x4000009B

#define HV_X64_MSR_SINT12			0x4000009C

#define HV_X64_MSR_SINT13			0x4000009D

#define HV_X64_MSR_SINT14			0x4000009E

#define HV_X64_MSR_SINT15			0x4000009F



/*

 * Define synthetic interrupt controller model specific registers for

 * nested hypervisor.

 */

#define HV_REGISTER_NESTED_SCONTROL            0x40001080

#define HV_REGISTER_NESTED_SVERSION            0x40001081

#define HV_REGISTER_NESTED_SIEFP               0x40001082

#define HV_REGISTER_NESTED_SIMP                0x40001083

#define HV_REGISTER_NESTED_EOM                 0x40001084

#define HV_REGISTER_NESTED_SINT0               0x40001090

#define HV_X64_MSR_NESTED_SCONTROL		0x40001080

#define HV_X64_MSR_NESTED_SVERSION		0x40001081

#define HV_X64_MSR_NESTED_SIEFP			0x40001082

#define HV_X64_MSR_NESTED_SIMP			0x40001083

#define HV_X64_MSR_NESTED_EOM			0x40001084

#define HV_X64_MSR_NESTED_SINT0			0x40001090



/*

 * Synthetic Timer MSRs. Four timers per vcpu.

 */

#define HV_REGISTER_STIMER0_CONFIG		0x400000B0

#define HV_REGISTER_STIMER0_COUNT		0x400000B1

#define HV_REGISTER_STIMER1_CONFIG		0x400000B2

#define HV_REGISTER_STIMER1_COUNT		0x400000B3

#define HV_REGISTER_STIMER2_CONFIG		0x400000B4

#define HV_REGISTER_STIMER2_COUNT		0x400000B5

#define HV_REGISTER_STIMER3_CONFIG		0x400000B6

#define HV_REGISTER_STIMER3_COUNT		0x400000B7

#define HV_X64_MSR_STIMER0_CONFIG		0x400000B0

#define HV_X64_MSR_STIMER0_COUNT		0x400000B1

#define HV_X64_MSR_STIMER1_CONFIG		0x400000B2

#define HV_X64_MSR_STIMER1_COUNT		0x400000B3

#define HV_X64_MSR_STIMER2_CONFIG		0x400000B4

#define HV_X64_MSR_STIMER2_COUNT		0x400000B5

#define HV_X64_MSR_STIMER3_CONFIG		0x400000B6

#define HV_X64_MSR_STIMER3_COUNT		0x400000B7



/* Hyper-V guest idle MSR */

#define HV_X64_MSR_GUEST_IDLE			0x400000F0



/* Hyper-V guest crash notification MSR's */

#define HV_REGISTER_CRASH_P0			0x40000100

#define HV_REGISTER_CRASH_P1			0x40000101

#define HV_REGISTER_CRASH_P2			0x40000102

#define HV_REGISTER_CRASH_P3			0x40000103

#define HV_REGISTER_CRASH_P4			0x40000104

#define HV_REGISTER_CRASH_CTL			0x40000105

#define HV_X64_MSR_CRASH_P0			0x40000100

#define HV_X64_MSR_CRASH_P1			0x40000101

#define HV_X64_MSR_CRASH_P2			0x40000102

#define HV_X64_MSR_CRASH_P3			0x40000103

#define HV_X64_MSR_CRASH_P4			0x40000104

#define HV_X64_MSR_CRASH_CTL			0x40000105



/* TSC emulation after migration */

#define HV_X64_MSR_REENLIGHTENMENT_CONTROL	0x40000106
@@ -276,31 +276,38 @@ enum hv_isolation_type { 
/* HV_X64_MSR_TSC_INVARIANT_CONTROL bits */

#define HV_EXPOSE_INVARIANT_TSC		BIT_ULL(0)



/* Register name aliases for temporary compatibility */

#define HV_X64_MSR_STIMER0_COUNT	HV_REGISTER_STIMER0_COUNT

#define HV_X64_MSR_STIMER0_CONFIG	HV_REGISTER_STIMER0_CONFIG

#define HV_X64_MSR_STIMER1_COUNT	HV_REGISTER_STIMER1_COUNT

#define HV_X64_MSR_STIMER1_CONFIG	HV_REGISTER_STIMER1_CONFIG

#define HV_X64_MSR_STIMER2_COUNT	HV_REGISTER_STIMER2_COUNT

#define HV_X64_MSR_STIMER2_CONFIG	HV_REGISTER_STIMER2_CONFIG

#define HV_X64_MSR_STIMER3_COUNT	HV_REGISTER_STIMER3_COUNT

#define HV_X64_MSR_STIMER3_CONFIG	HV_REGISTER_STIMER3_CONFIG

#define HV_X64_MSR_SCONTROL		HV_REGISTER_SCONTROL

#define HV_X64_MSR_SVERSION		HV_REGISTER_SVERSION

#define HV_X64_MSR_SIMP			HV_REGISTER_SIMP

#define HV_X64_MSR_SIEFP		HV_REGISTER_SIEFP

#define HV_X64_MSR_VP_INDEX		HV_REGISTER_VP_INDEX

#define HV_X64_MSR_EOM			HV_REGISTER_EOM

#define HV_X64_MSR_SINT0		HV_REGISTER_SINT0

#define HV_X64_MSR_SINT15		HV_REGISTER_SINT15

#define HV_X64_MSR_CRASH_P0		HV_REGISTER_CRASH_P0

#define HV_X64_MSR_CRASH_P1		HV_REGISTER_CRASH_P1

#define HV_X64_MSR_CRASH_P2		HV_REGISTER_CRASH_P2

#define HV_X64_MSR_CRASH_P3		HV_REGISTER_CRASH_P3

#define HV_X64_MSR_CRASH_P4		HV_REGISTER_CRASH_P4

#define HV_X64_MSR_CRASH_CTL		HV_REGISTER_CRASH_CTL

#define HV_X64_MSR_TIME_REF_COUNT	HV_REGISTER_TIME_REF_COUNT

#define HV_X64_MSR_REFERENCE_TSC	HV_REGISTER_REFERENCE_TSC

/*

 * To support arch-generic code calling hv_set/get_register:

 * - On x86, HV_MSR_ indicates an MSR accessed via rdmsrl/wrmsrl

 * - On ARM, HV_MSR_ indicates a VP register accessed via hypercall

 */

#define HV_MSR_CRASH_P0		(HV_X64_MSR_CRASH_P0)

#define HV_MSR_CRASH_P1		(HV_X64_MSR_CRASH_P1)

#define HV_MSR_CRASH_P2		(HV_X64_MSR_CRASH_P2)

#define HV_MSR_CRASH_P3		(HV_X64_MSR_CRASH_P3)

#define HV_MSR_CRASH_P4		(HV_X64_MSR_CRASH_P4)

#define HV_MSR_CRASH_CTL	(HV_X64_MSR_CRASH_CTL)



#define HV_MSR_VP_INDEX		(HV_X64_MSR_VP_INDEX)

#define HV_MSR_TIME_REF_COUNT	(HV_X64_MSR_TIME_REF_COUNT)

#define HV_MSR_REFERENCE_TSC	(HV_X64_MSR_REFERENCE_TSC)



#define HV_MSR_SINT0		(HV_X64_MSR_SINT0)

#define HV_MSR_SVERSION		(HV_X64_MSR_SVERSION)

#define HV_MSR_SCONTROL		(HV_X64_MSR_SCONTROL)

#define HV_MSR_SIEFP		(HV_X64_MSR_SIEFP)

#define HV_MSR_SIMP		(HV_X64_MSR_SIMP)

#define HV_MSR_EOM		(HV_X64_MSR_EOM)



#define HV_MSR_NESTED_SCONTROL	(HV_X64_MSR_NESTED_SCONTROL)

#define HV_MSR_NESTED_SVERSION	(HV_X64_MSR_NESTED_SVERSION)

#define HV_MSR_NESTED_SIEFP	(HV_X64_MSR_NESTED_SIEFP)

#define HV_MSR_NESTED_SIMP	(HV_X64_MSR_NESTED_SIMP)

#define HV_MSR_NESTED_EOM	(HV_X64_MSR_NESTED_EOM)

#define HV_MSR_NESTED_SINT0	(HV_X64_MSR_NESTED_SINT0)



#define HV_MSR_STIMER0_CONFIG	(HV_X64_MSR_STIMER0_CONFIG)

#define HV_MSR_STIMER0_COUNT	(HV_X64_MSR_STIMER0_COUNT)



/*

 * Registers are only accessible via HVCALL_GET_VP_REGISTERS hvcall and

arch/x86/include/asm/mshyperv.h

+15 −15
Original line number Diff line number Diff line
@@ -293,24 +293,24 @@ static inline void hv_ivm_msr_write(u64 msr, u64 value) {} 
static inline void hv_ivm_msr_read(u64 msr, u64 *value) {}

#endif



static inline bool hv_is_synic_reg(unsigned int reg)

static inline bool hv_is_synic_msr(unsigned int reg)

{

	return (reg >= HV_REGISTER_SCONTROL) &&

	       (reg <= HV_REGISTER_SINT15);

	return (reg >= HV_X64_MSR_SCONTROL) &&

	       (reg <= HV_X64_MSR_SINT15);

}



static inline bool hv_is_sint_reg(unsigned int reg)

static inline bool hv_is_sint_msr(unsigned int reg)

{

	return (reg >= HV_REGISTER_SINT0) &&

	       (reg <= HV_REGISTER_SINT15);

	return (reg >= HV_X64_MSR_SINT0) &&

	       (reg <= HV_X64_MSR_SINT15);

}



u64 hv_get_register(unsigned int reg);

void hv_set_register(unsigned int reg, u64 value);

u64 hv_get_non_nested_register(unsigned int reg);

void hv_set_non_nested_register(unsigned int reg, u64 value);

u64 hv_get_msr(unsigned int reg);

void hv_set_msr(unsigned int reg, u64 value);

u64 hv_get_non_nested_msr(unsigned int reg);

void hv_set_non_nested_msr(unsigned int reg, u64 value);



static __always_inline u64 hv_raw_get_register(unsigned int reg)

static __always_inline u64 hv_raw_get_msr(unsigned int reg)

{

	return __rdmsr(reg);

}
@@ -331,10 +331,10 @@ static inline int hyperv_flush_guest_mapping_range(u64 as, 
{

	return -1;

}

static inline void hv_set_register(unsigned int reg, u64 value) { }

static inline u64 hv_get_register(unsigned int reg) { return 0; }

static inline void hv_set_non_nested_register(unsigned int reg, u64 value) { }

static inline u64 hv_get_non_nested_register(unsigned int reg) { return 0; }

static inline void hv_set_msr(unsigned int reg, u64 value) { }

static inline u64 hv_get_msr(unsigned int reg) { return 0; }

static inline void hv_set_non_nested_msr(unsigned int reg, u64 value) { }

static inline u64 hv_get_non_nested_msr(unsigned int reg) { return 0; }

#endif /* CONFIG_HYPERV */