clk: qcom: alpha-pll: convert from round_rate() to determine_rate()

					clk_alpha_pll_hwfsm_is_enabled);

}

static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,

				     unsigned long *prate)

static int clk_alpha_pll_determine_rate(struct clk_hw *hw,

					struct clk_rate_request *req)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	u32 l, alpha_width = pll_alpha_width(pll);

	u64 a;

	unsigned long min_freq, max_freq;

	rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);

	if (!pll->vco_table || alpha_pll_find_vco(pll, rate))

		return rate;

	req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, &l,

					 &a, alpha_width);

	if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate))

		return 0;

	min_freq = pll->vco_table[0].min_freq;

	max_freq = pll->vco_table[pll->num_vco - 1].max_freq;

	return clamp(rate, min_freq, max_freq);

	req->rate = clamp(req->rate, min_freq, max_freq);

	return 0;

}

void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

	return 0;

}

static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,

					unsigned long *prate)

static int alpha_pll_huayra_determine_rate(struct clk_hw *hw,

					   struct clk_rate_request *req)

{

	u32 l, a;

	return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);

	req->rate = alpha_huayra_pll_round_rate(req->rate,

						req->best_parent_rate, &l, &a);

	return 0;

}

static int trion_pll_is_enabled(struct clk_alpha_pll *pll,

	.disable = clk_alpha_pll_disable,

	.is_enabled = clk_alpha_pll_is_enabled,

	.recalc_rate = clk_alpha_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.determine_rate = clk_alpha_pll_determine_rate,

	.set_rate = clk_alpha_pll_set_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);

	.disable = clk_alpha_pll_disable,

	.is_enabled = clk_alpha_pll_is_enabled,

	.recalc_rate = alpha_pll_huayra_recalc_rate,

	.round_rate = alpha_pll_huayra_round_rate,

	.determine_rate = alpha_pll_huayra_determine_rate,

	.set_rate = alpha_pll_huayra_set_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);

	.disable = clk_alpha_pll_hwfsm_disable,

	.is_enabled = clk_alpha_pll_hwfsm_is_enabled,

	.recalc_rate = clk_alpha_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.determine_rate = clk_alpha_pll_determine_rate,

	.set_rate = clk_alpha_pll_hwfsm_set_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);

	.disable = clk_trion_pll_disable,

	.is_enabled = clk_trion_pll_is_enabled,

	.recalc_rate = clk_trion_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.determine_rate = clk_alpha_pll_determine_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops);

	{ }

};

static long

clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,

				 unsigned long *prate)

static int clk_alpha_pll_postdiv_determine_rate(struct clk_hw *hw,

						struct clk_rate_request *req)

{

	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);

	const struct clk_div_table *table;

	else

		table = clk_alpha_div_table;

	return divider_round_rate(hw, rate, prate, table,

				  pll->width, CLK_DIVIDER_POWER_OF_TWO);

	req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,

				       table, pll->width,

				       CLK_DIVIDER_POWER_OF_TWO);

	return 0;

}

static long

clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,

				    unsigned long *prate)

static int clk_alpha_pll_postdiv_ro_determine_rate(struct clk_hw *hw,

						   struct clk_rate_request *req)

{

	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);

	u32 ctl, div;

	div = 1 << fls(ctl);

	if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)

		*prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);

		req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),

							  div * req->rate);

	req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);

	return DIV_ROUND_UP_ULL((u64)*prate, div);

	return 0;

}

static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,

const struct clk_ops clk_alpha_pll_postdiv_ops = {

	.recalc_rate = clk_alpha_pll_postdiv_recalc_rate,

	.round_rate = clk_alpha_pll_postdiv_round_rate,

	.determine_rate = clk_alpha_pll_postdiv_determine_rate,

	.set_rate = clk_alpha_pll_postdiv_set_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);

const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {

	.round_rate = clk_alpha_pll_postdiv_round_ro_rate,

	.determine_rate = clk_alpha_pll_postdiv_ro_determine_rate,

	.recalc_rate = clk_alpha_pll_postdiv_recalc_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);

	.is_enabled = clk_alpha_pll_is_enabled,

	.set_rate = alpha_pll_fabia_set_rate,

	.recalc_rate = alpha_pll_fabia_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.determine_rate = clk_alpha_pll_determine_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);

	.disable = alpha_pll_fabia_disable,

	.is_enabled = clk_alpha_pll_is_enabled,

	.recalc_rate = alpha_pll_fabia_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.determine_rate = clk_alpha_pll_determine_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);

	return (parent_rate / div);

}

static long

clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,

				 unsigned long *prate)

static int clk_trion_pll_postdiv_determine_rate(struct clk_hw *hw,

						struct clk_rate_request *req)

{

	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);

	return divider_round_rate(hw, rate, prate, pll->post_div_table,

	req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,

				       pll->post_div_table,

				       pll->width, CLK_DIVIDER_ROUND_CLOSEST);

	return 0;

};

static int

const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {

	.recalc_rate = clk_trion_pll_postdiv_recalc_rate,

	.round_rate = clk_trion_pll_postdiv_round_rate,

	.determine_rate = clk_trion_pll_postdiv_determine_rate,

	.set_rate = clk_trion_pll_postdiv_set_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops);

static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,

				unsigned long rate, unsigned long *prate)

static int clk_alpha_pll_postdiv_fabia_determine_rate(struct clk_hw *hw,

						      struct clk_rate_request *req)

{

	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);

	return divider_round_rate(hw, rate, prate, pll->post_div_table,

	req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,

				       pll->post_div_table,

				       pll->width, CLK_DIVIDER_ROUND_CLOSEST);

	return 0;

}

static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,

const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {

	.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,

	.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,

	.determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate,

	.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);

	.disable = clk_trion_pll_disable,

	.is_enabled = clk_trion_pll_is_enabled,

	.recalc_rate = clk_trion_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.determine_rate = clk_alpha_pll_determine_rate,

	.set_rate = alpha_pll_trion_set_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops);

	.disable = clk_trion_pll_disable,

	.is_enabled = clk_trion_pll_is_enabled,

	.recalc_rate = clk_trion_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.determine_rate = clk_alpha_pll_determine_rate,

	.set_rate = alpha_pll_trion_set_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);

const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {

	.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,

	.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,

	.determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate,

	.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);

	.disable = clk_alpha_pll_disable,

	.is_enabled = clk_alpha_pll_is_enabled,

	.recalc_rate = alpha_pll_fabia_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.determine_rate = clk_alpha_pll_determine_rate,

	.set_rate = clk_alpha_pll_agera_set_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);

	.disable = alpha_pll_lucid_5lpe_disable,

	.is_enabled = clk_trion_pll_is_enabled,

	.recalc_rate = clk_trion_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.determine_rate = clk_alpha_pll_determine_rate,

	.set_rate = alpha_pll_lucid_5lpe_set_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops);

	.disable = alpha_pll_lucid_5lpe_disable,

	.is_enabled = clk_trion_pll_is_enabled,

	.recalc_rate = clk_trion_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.determine_rate = clk_alpha_pll_determine_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops);

const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {

	.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,

	.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,

	.determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate,

	.set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops);

	.disable = clk_zonda_pll_disable,

	.is_enabled = clk_trion_pll_is_enabled,

	.recalc_rate = clk_trion_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.determine_rate = clk_alpha_pll_determine_rate,

	.set_rate = clk_zonda_pll_set_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops);

	.disable = alpha_pll_lucid_evo_disable,

	.is_enabled = clk_trion_pll_is_enabled,

	.recalc_rate = alpha_pll_lucid_evo_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.determine_rate = clk_alpha_pll_determine_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops);

const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = {

	.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,

	.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,

	.determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate,

	.set_rate = clk_lucid_evo_pll_postdiv_set_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops);

	.disable = alpha_pll_lucid_evo_disable,

	.is_enabled = clk_trion_pll_is_enabled,

	.recalc_rate = alpha_pll_lucid_evo_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.determine_rate = clk_alpha_pll_determine_rate,

	.set_rate = alpha_pll_lucid_5lpe_set_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops);

	.disable = alpha_pll_reset_lucid_evo_disable,

	.is_enabled = clk_trion_pll_is_enabled,

	.recalc_rate = alpha_pll_lucid_evo_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.determine_rate = clk_alpha_pll_determine_rate,

	.set_rate = alpha_pll_lucid_5lpe_set_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops);

	return parent_rate * l;

}

static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate,

					  unsigned long *prate)

static int clk_rivian_evo_pll_determine_rate(struct clk_hw *hw,

					     struct clk_rate_request *req)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	unsigned long min_freq, max_freq;

	u32 l;

	u64 a;

	rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0);

	if (!pll->vco_table || alpha_pll_find_vco(pll, rate))

		return rate;

	req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, &l,

					 &a, 0);

	if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate))

		return 0;

	min_freq = pll->vco_table[0].min_freq;

	max_freq = pll->vco_table[pll->num_vco - 1].max_freq;

	return clamp(rate, min_freq, max_freq);

	req->rate = clamp(req->rate, min_freq, max_freq);

	return 0;

}

const struct clk_ops clk_alpha_pll_rivian_evo_ops = {

	.disable = alpha_pll_lucid_5lpe_disable,

	.is_enabled = clk_trion_pll_is_enabled,

	.recalc_rate = clk_rivian_evo_pll_recalc_rate,

	.round_rate = clk_rivian_evo_pll_round_rate,

	.determine_rate = clk_rivian_evo_pll_determine_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops);

	.disable = clk_zonda_pll_disable,

	.is_enabled = clk_alpha_pll_is_enabled,

	.recalc_rate = clk_trion_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.determine_rate = clk_alpha_pll_determine_rate,

	.set_rate = clk_zonda_pll_set_rate,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops);

	.enable = clk_alpha_pll_slew_enable,

	.disable = clk_alpha_pll_disable,

	.recalc_rate = clk_alpha_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.determine_rate = clk_alpha_pll_determine_rate,

	.set_rate = clk_alpha_pll_slew_set_rate,

};

EXPORT_SYMBOL(clk_alpha_pll_slew_ops);