Commit 0edaa459 authored by Chen Wang's avatar Chen Wang Committed by Thomas Gleixner
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riscv: sophgo: dts: Add msi controller for SG2042

parent c6674154
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+10 −0
Original line number Diff line number Diff line
@@ -173,6 +173,16 @@ pllclk: clock-controller@70300100c0 {
			#clock-cells = <1>;
		};

		msi: msi-controller@7030010304 {
			compatible = "sophgo,sg2042-msi";
			reg = <0x70 0x30010304 0x0 0x4>,
			      <0x70 0x30010300 0x0 0x4>;
			reg-names = "clr", "doorbell";
			msi-controller;
			#msi-cells = <0>;
			msi-ranges = <&intc 64 IRQ_TYPE_LEVEL_HIGH 32>;
		};

		rpgate: clock-controller@7030010368 {
			compatible = "sophgo,sg2042-rpgate";
			reg = <0x70 0x30010368 0x0 0x98>;