Commit 0f051749 authored by Krishna Chaitanya Chundru's avatar Krishna Chaitanya Chundru Committed by Vinod Koul
Browse files

phy: qcom-qmp-pcie: add dual lane PHY support for SM8750 



The PCIe Gen3 x2 PHY for SM8750 uses new phy, add the
required registers and offsets for this phy.

Signed-off-by: default avatarKrishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250809-pakala-v1-2-abf1c416dbaa@oss.qualcomm.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent edafd4f3

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

+149 −0
Original line number Diff line number Diff line
@@ -93,6 +93,13 @@ static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = { 
	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V6_PCS_POWER_DOWN_CONTROL,

};



static const unsigned int pciephy_v7_regs_layout[QPHY_LAYOUT_SIZE] = {

	[QPHY_SW_RESET]			= QPHY_V7_PCS_SW_RESET,

	[QPHY_START_CTRL]		= QPHY_V7_PCS_START_CONTROL,

	[QPHY_PCS_STATUS]		= QPHY_V7_PCS_PCS_STATUS1,

	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V7_PCS_POWER_DOWN_CONTROL,

};



static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
@@ -2590,6 +2597,108 @@ static const struct qmp_phy_init_tbl sm8650_qmp_gen4x2_pcie_rx_tbl[] = { 
	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),

};



static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_EN_CENTER, 0x1),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER1, 0x62),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER2, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE0, 0xf8),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE0, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE1, 0x93),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE1, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_CLK_ENABLE1, 0x90),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYS_CLK_CTRL, 0x82),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_IVCO, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE0, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE1, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE0, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE1, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE0, 0x36),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE1, 0x36),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_EN_SEL, 0x08),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_BG_TIMER, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP_EN, 0x42),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE0, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE0, 0x0d),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE1, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE1, 0x1a),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE0, 0x41),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE1, 0x34),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE0, 0xab),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE0, 0xaa),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE0, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE1, 0x55),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE1, 0x55),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE1, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE_MAP, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_CLK_SELECT, 0x34),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_HSCLK_SEL_1, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORECLK_DIV_MODE1, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_CMN_CONFIG_1, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_ADDITIONAL_MISC_3,	0x0F),

	QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORE_CLK_EN, 0xA0),

};



static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_rx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_GM_CAL, 0x11),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH,	0xBF),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH2, 0xBF),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH3, 0xB7),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH4, 0xEA),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_LOW, 0x3F),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH, 0x09),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH2, 0x49),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH3, 0x1B),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH4, 0x9C),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_LOW, 0xD1),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_HIGH, 0x09),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_HIGH2, 0x49),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_HIGH3, 0x1B),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_HIGH4, 0x9C),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_LOW, 0xD1),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_TX_ADAPT_PRE_THRESH1, 0x3E),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_TX_ADAPT_PRE_THRESH2, 0x1E),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_TX_ADAPT_POST_THRESH, 0xD2),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FO_GAIN, 0x09),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_GAIN, 0x05),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH1, 0x08),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH2, 0x08),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL2, 0x09),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_ENABLES, 0x1C),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CNTRL, 0x60),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_TRIM, 0x08),

};



static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_tx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_1,	0x35),

	QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_3,	0x10),

	QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_4,	0x31),

	QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_5,	0x7F),

	QMP_PHY_INIT_CFG(QSERDES_V7_TX_PI_QEC_CTRL,	0x02),

	QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x08),

	QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x14),

};



static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_pcs_tbl[] = {

	QMP_PHY_INIT_CFG(QPHY_V7_PCS_REFGEN_REQ_CONFIG1, 0x05),

	QMP_PHY_INIT_CFG(QPHY_V7_PCS_RX_SIGDET_LVL, 0x77),

	QMP_PHY_INIT_CFG(QPHY_V7_PCS_RATE_SLEW_CNTRL1, 0x0B),

	QMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG2, 0x0F),

	QMP_PHY_INIT_CFG(QPHY_V7_PCS_PCS_TX_RX_CONFIG, 0x8C),

	QMP_PHY_INIT_CFG(QPHY_V7_PCS_G12S1_TXDEEMPH_M6DB, 0x17),

	QMP_PHY_INIT_CFG(QPHY_V7_PCS_G3S2_PRE_GAIN,	0x2E),

};



static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_pcs_misc_tbl[] = {

	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1E),

	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME, 0x27),

	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1D),

	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),

	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xC1),

	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),

};



static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
@@ -3207,6 +3316,16 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_30 = { 
	.rx2		= 0x3a00,

};



static const struct qmp_pcie_offsets qmp_pcie_offsets_v7 = {

	.serdes		= 0x0,

	.pcs		= 0x400,

	.pcs_misc	= 0x800,

	.tx		= 0x1000,

	.rx		= 0x1200,

	.tx2		= 0x1800,

	.rx2		= 0x1a00,

};



static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = {

	.serdes		= 0x1000,

	.pcs		= 0x1200,
@@ -3996,6 +4115,33 @@ static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = { 
	.phy_status		= PHYSTATUS,

};



static const struct qmp_phy_cfg sm8750_qmp_gen3x2_pciephy_cfg = {

	.lanes = 2,



	.offsets		= &qmp_pcie_offsets_v7,



	.tbls = {

		.serdes		= sm8750_qmp_gen3x2_pcie_serdes_tbl,

		.serdes_num	= ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_serdes_tbl),

		.tx		= sm8750_qmp_gen3x2_pcie_tx_tbl,

		.tx_num		= ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_tx_tbl),

		.rx		= sm8750_qmp_gen3x2_pcie_rx_tbl,

		.rx_num		= ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_rx_tbl),

		.pcs		= sm8750_qmp_gen3x2_pcie_pcs_tbl,

		.pcs_num	= ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_pcs_tbl),

		.pcs_misc	= sm8750_qmp_gen3x2_pcie_pcs_misc_tbl,

		.pcs_misc_num	= ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_pcs_misc_tbl),

	},

	.reset_list		= sdm845_pciephy_reset_l,

	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),

	.vreg_list		= qmp_phy_vreg_l,

	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),

	.regs			= pciephy_v7_regs_layout,



	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,

	.phy_status		= PHYSTATUS,

};



static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = {

	.lanes = 2,
@@ -5099,6 +5245,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { 
	}, {

		.compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy",

		.data = &sm8650_qmp_gen4x2_pciephy_cfg,

	}, {

		.compatible = "qcom,sm8750-qmp-gen3x2-pcie-phy",

		.data = &sm8750_qmp_gen3x2_pciephy_cfg,

	}, {

		.compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy",

		.data = &sm8550_qmp_gen3x2_pciephy_cfg,

drivers/phy/qualcomm/phy-qcom-qmp-pcs-v7.h

+2 −0
Original line number Diff line number Diff line
@@ -17,6 +17,8 @@ 
#define QPHY_V7_PCS_LOCK_DETECT_CONFIG3		0x0cc

#define QPHY_V7_PCS_LOCK_DETECT_CONFIG6		0x0d8

#define QPHY_V7_PCS_REFGEN_REQ_CONFIG1		0x0dc

#define QPHY_V7_PCS_G12S1_TXDEEMPH_M6DB		0x168

#define QPHY_V7_PCS_G3S2_PRE_GAIN		0x170

#define QPHY_V7_PCS_RX_SIGDET_LVL		0x188

#define QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_L	0x190

#define QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_H	0x194

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h

+3 −1
Original line number Diff line number Diff line
@@ -40,6 +40,8 @@ 
#define QSERDES_V7_RX_UCDR_SB2_GAIN1				0x54

#define QSERDES_V7_RX_UCDR_SB2_GAIN2				0x58

#define QSERDES_V7_RX_AUX_DATA_TCOARSE_TFINE			0x60

#define QSERDES_V7_RX_TX_ADAPT_PRE_THRESH1			0xc4

#define QSERDES_V7_RX_TX_ADAPT_PRE_THRESH2			0xc8

#define QSERDES_V7_RX_TX_ADAPT_POST_THRESH			0xcc

#define QSERDES_V7_RX_VGA_CAL_CNTRL1				0xd4

#define QSERDES_V7_RX_VGA_CAL_CNTRL2				0xd8
@@ -50,7 +52,7 @@ 
#define QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW			0xf8

#define QSERDES_V7_RX_RX_IDAC_TSETTLE_HIGH			0xfc

#define QSERDES_V7_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1		0x110

#define QSERDES_V7_RX_SIDGET_ENABLES				0x118

#define QSERDES_V7_RX_SIGDET_ENABLES				0x118

#define QSERDES_V7_RX_SIGDET_CNTRL				0x11c

#define QSERDES_V7_RX_SIGDET_DEGLITCH_CNTRL			0x124

#define QSERDES_V7_RX_RX_MODE_00_LOW				0x15c