Commit 0f46f508 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'soc-drivers-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull SoC driver updates from Arnd Bergmann:
 "Changes are all over the place, but very little sticks out as
  noteworthy.

  There is a new misc driver for the Raspberry Pi 5's RP1 multifunction
  I/O chip, along with hooking it up to the pinctrl and clk frameworks.

  The reset controller and memory subsystems have mainly small updates,
  but there are two new reset drivers for the K230 and VC1800B SoCs, and
  new memory driver support for Tegra264.

  The ARM SMCCC and SCMI firmware drivers gain a few more features that
  should help them be supported across more environments. Similarly, the
  SoC specific firmware on Tegra and Qualcomm get minor enhancements and
  chip support.

  In the drivers/soc/ directory, the ASPEED LPC snoop driver gets an
  overhaul for code robustness, the Tegra and Qualcomm and NXP drivers
  grow to support more chips, while the Hisilicon, Mediatek and Renesas
  drivers see mostly janitorial fixes"

* tag 'soc-drivers-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (100 commits)
  bus: del unnecessary init var
  soc: fsl: qe: convert set_multiple() to returning an integer
  pinctrl: rp1: use new GPIO line value setter callbacks
  soc: hisilicon: kunpeng_hccs: Fix incorrect log information
  dt-bindings: soc: qcom: qcom,pmic-glink: document Milos compatible
  dt-bindings: soc: qcom,aoss-qmp: document the Milos Always-On Subsystem side channel
  dt-bindings: firmware: qcom,scm: document Milos SCM Firmware Interface
  soc: qcom: socinfo: Add support to retrieve APPSBL build details
  soc: qcom: pmic_glink: fix OF node leak
  soc: qcom: spmi-pmic: add more PMIC SUBTYPE IDs
  soc: qcom: socinfo: Add PM7550 & PMIV0108 PMICs
  soc: qcom: socinfo: Add SoC IDs for SM7635 family
  dt-bindings: arm: qcom,ids: Add SoC IDs for SM7635 family
  firmware: qcom: scm: request the waitqueue irq *after* initializing SCM
  firmware: qcom: scm: initialize tzmem before marking SCM as available
  firmware: qcom: scm: take struct device as argument in SHM bridge enable
  firmware: qcom: scm: remove unused arguments from SHM bridge routines
  soc: qcom: rpmh-rsc: Add RSC version 4 support
  memory: tegra: Add Tegra264 MC and EMC support
  firmware: tegra: bpmp: Fix build failure for tegra264-only config
  ...
parents 115e74a2 4507d205

Documentation/devicetree/bindings/arm/cpus.yaml

+1 −0
Original line number Diff line number Diff line
@@ -200,6 +200,7 @@ properties: 
      - qcom,kryo385

      - qcom,kryo465

      - qcom,kryo468

      - qcom,kryo470

      - qcom,kryo485

      - qcom,kryo560

      - qcom,kryo570

Documentation/devicetree/bindings/firmware/qcom,scm.yaml

+2 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ properties: 
          - qcom,scm-ipq8074

          - qcom,scm-ipq9574

          - qcom,scm-mdm9607

          - qcom,scm-milos

          - qcom,scm-msm8226

          - qcom,scm-msm8660

          - qcom,scm-msm8916
@@ -198,6 +199,7 @@ allOf: 
          compatible:

            contains:

              enum:

                - qcom,scm-milos

                - qcom,scm-sm8450

                - qcom,scm-sm8550

                - qcom,scm-sm8650

Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt

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* Device tree bindings for ARM PL172/PL175/PL176 MultiPort Memory Controller



Required properties:



- compatible:		Must be "arm,primecell" and exactly one from

			"arm,pl172", "arm,pl175" or "arm,pl176".



- reg:			Must contains offset/length value for controller.



- #address-cells:	Must be 2. The partition number has to be encoded in the

			first address cell and it may accept values 0..N-1

			(N - total number of partitions). The second cell is the

			offset into the partition.



- #size-cells:		Must be set to 1.



- ranges:		Must contain one or more chip select memory regions.



- clocks:		Must contain references to controller clocks.



- clock-names:		Must contain "mpmcclk" and "apb_pclk".



- clock-ranges:		Empty property indicating that child nodes can inherit

			named clocks. Required only if clock tree data present

			in device tree.

			See clock-bindings.txt



Child chip-select (cs) nodes contain the memory devices nodes connected to

such as NOR (e.g. cfi-flash) and NAND.



Required child cs node properties:



- #address-cells:	Must be 2.



- #size-cells:		Must be 1.



- ranges:		Empty property indicating that child nodes can inherit

			memory layout.



- clock-ranges:		Empty property indicating that child nodes can inherit

			named clocks. Required only if clock tree data present

			in device tree.



- mpmc,cs:		Chip select number. Indicates to the pl0172 driver

			which chipselect is used for accessing the memory.



- mpmc,memory-width:	Width of the chip select memory. Must be equal to

			either 8, 16 or 32.



Optional child cs node config properties:



- mpmc,async-page-mode:	Enable asynchronous page mode.



- mpmc,cs-active-high:	Set chip select polarity to active high.



- mpmc,byte-lane-low:	Set byte lane state to low.



- mpmc,extended-wait:	Enable extended wait.



- mpmc,buffer-enable:	Enable write buffer, option is not supported by

			PL175 and PL176 controllers.



- mpmc,write-protect:	Enable write protect.



Optional child cs node timing properties:



- mpmc,write-enable-delay:	Delay from chip select assertion to write

				enable (WE signal) in nano seconds.



- mpmc,output-enable-delay:	Delay from chip select assertion to output

				enable (OE signal) in nano seconds.



- mpmc,write-access-delay:	Delay from chip select assertion to write

				access in nano seconds.



- mpmc,read-access-delay:	Delay from chip select assertion to read

				access in nano seconds.



- mpmc,page-mode-read-delay:	Delay for asynchronous page mode sequential

				accesses in nano seconds.



- mpmc,turn-round-delay:	Delay between access to memory banks in nano

				seconds.



If any of the above timing parameters are absent, current parameter value will

be taken from the corresponding HW reg.



Example for pl172 with nor flash on chip select 0 shown below.



emc: memory-controller@40005000 {

	compatible = "arm,pl172", "arm,primecell";

	reg = <0x40005000 0x1000>;

	clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;

	clock-names = "mpmcclk", "apb_pclk";

	#address-cells = <2>;

	#size-cells = <1>;

	ranges = <0 0 0x1c000000 0x1000000

		  1 0 0x1d000000 0x1000000

		  2 0 0x1e000000 0x1000000

		  3 0 0x1f000000 0x1000000>;



	cs0 {

		#address-cells = <2>;

		#size-cells = <1>;

		ranges;



		mpmc,cs = <0>;

		mpmc,memory-width = <16>;

		mpmc,byte-lane-low;

		mpmc,write-enable-delay = <0>;

		mpmc,output-enable-delay = <0>;

		mpmc,read-enable-delay = <70>;

		mpmc,page-mode-read-delay = <70>;



		flash@0,0 {

			compatible = "sst,sst39vf320", "cfi-flash";

			reg = <0 0 0x400000>;

			bank-width = <2>;

			#address-cells = <1>;

			#size-cells = <1>;

			partition@0 {

				label = "data";

				reg = <0 0x400000>;

			};

		};

	};

};

Documentation/devicetree/bindings/memory-controllers/arm,pl172.yaml

0 → 100644
+222 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/arm,pl172.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: ARM PL172/PL175/PL176 MultiPort Memory Controller



maintainers:

  - Frank Li <Frank.Li@nxp.com>



# We need a select here so we don't match all nodes with 'arm,primecell'

select:

  properties:

    compatible:

      contains:

        enum:

          - arm,pl172

          - arm,pl175

          - arm,pl176

  required:

    - compatible



properties:

  compatible:

    items:

      - enum:

          - arm,pl172

          - arm,pl175

          - arm,pl176

      - const: arm,primecell



  reg:

    maxItems: 1



  '#address-cells':

    const: 2



  '#size-cells':

    const: 1



  ranges: true



  clocks:

    maxItems: 2



  clock-names:

    items:

      - const: mpmcclk

      - const: apb_pclk



  clock-ranges: true



  resets:

    maxItems: 1



patternProperties:

  "^cs[0-9]$":

    type: object

    additionalProperties: false

    patternProperties:

      "^flash@[0-9],[0-9a-f]+$":

        type: object

        $ref: /schemas/mtd/mtd-physmap.yaml#

        unevaluatedProperties: false



      "^(gpio|sram)@[0-9],[0-9a-f]+$":

        type: object

        additionalProperties: true



    properties:

      '#address-cells':

        const: 2



      '#size-cells':

        const: 1



      ranges: true



      clocks:

        maxItems: 2



      clock-ranges: true



      mpmc,cs:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          Chip select number. Indicates to the pl0172 driver

          which chipselect is used for accessing the memory.



      mpmc,memory-width:

        $ref: /schemas/types.yaml#/definitions/uint32

        enum: [8, 16, 32]

        description:

          Width of the chip select memory. Must be equal to either 8, 16 or 32.



      mpmc,async-page-mode:

        $ref: /schemas/types.yaml#/definitions/flag

        description:

          Enable asynchronous page mode.



      mpmc,cs-active-high:

        $ref: /schemas/types.yaml#/definitions/flag

        description:

          Set chip select polarity to active high.



      mpmc,byte-lane-low:

        $ref: /schemas/types.yaml#/definitions/flag

        description:

          Set byte lane state to low.



      mpmc,extended-wait:

        $ref: /schemas/types.yaml#/definitions/flag

        description:

          Enable extended wait.



      mpmc,buffer-enable:

        $ref: /schemas/types.yaml#/definitions/flag

        description:

          Enable write buffer, option is not supported by

          PL175 and PL176 controllers.



      mpmc,write-protect:

        $ref: /schemas/types.yaml#/definitions/flag

        description:

          Enable write protect.



      mpmc,read-enable-delay:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          Delay from chip select assertion to read

          enable (RE signal) in nano seconds.



      mpmc,write-enable-delay:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          Delay from chip select assertion to write

          enable (WE signal) in nano seconds.



      mpmc,output-enable-delay:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          Delay from chip select assertion to output

          enable (OE signal) in nano seconds.



      mpmc,write-access-delay:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          Delay from chip select assertion to write

          access in nano seconds.



      mpmc,read-access-delay:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          Delay from chip select assertion to read

          access in nano seconds.



      mpmc,page-mode-read-delay:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          Delay for asynchronous page mode sequential

          accesses in nano seconds.



      mpmc,turn-round-delay:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          Delay between access to memory banks in nano

          seconds.



required:

  - compatible

  - reg

  - '#address-cells'

  - '#size-cells'

  - ranges

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/lpc18xx-ccu.h>



    memory-controller@40005000 {

        compatible = "arm,pl172", "arm,primecell";

        reg = <0x40005000 0x1000>;

        clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;

        clock-names = "mpmcclk", "apb_pclk";

        #address-cells = <2>;

        #size-cells = <1>;

        ranges = <0 0 0x1c000000 0x1000000

                  1 0 0x1d000000 0x1000000

                  2 0 0x1e000000 0x1000000

                  3 0 0x1f000000 0x1000000>;



        cs0 {

            #address-cells = <2>;

            #size-cells = <1>;

            ranges;



            mpmc,cs = <0>;

            mpmc,memory-width = <16>;

            mpmc,byte-lane-low;

            mpmc,write-enable-delay = <0>;

            mpmc,output-enable-delay = <0>;

            mpmc,read-enable-delay = <70>;

            mpmc,page-mode-read-delay = <70>;



            flash@0,0 {

                compatible = "sst,sst39vf320", "cfi-flash";

                reg = <0 0 0x400000>;

                bank-width = <2>;

                #address-cells = <1>;

                #size-cells = <1>;

                partition@0 {

                    label = "data";

                    reg = <0 0x400000>;

                };

            };

        };

    };

Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml

+34 −20
Original line number Diff line number Diff line
@@ -11,11 +11,10 @@ maintainers: 


properties:

  compatible:

    oneOf:

      - description: Revision > 2.1 controllers

        items:

          - enum:

          - brcm,brcmstb-memc-ddr-rev-b.1.x

          - brcm,brcmstb-memc-ddr-rev-b.2.0

          - brcm,brcmstb-memc-ddr-rev-b.2.1

              - brcm,brcmstb-memc-ddr-rev-b.2.2

              - brcm,brcmstb-memc-ddr-rev-b.2.3

              - brcm,brcmstb-memc-ddr-rev-b.2.5
@@ -29,6 +28,19 @@ properties: 
              - brcm,brcmstb-memc-ddr-rev-c.1.2

              - brcm,brcmstb-memc-ddr-rev-c.1.3

              - brcm,brcmstb-memc-ddr-rev-c.1.4

          - const: brcm,brcmstb-memc-ddr-rev-b.2.1

          - const: brcm,brcmstb-memc-ddr

      - description: Revision 2.1 controllers

        items:

          - const: brcm,brcmstb-memc-ddr-rev-b.2.1

          - const: brcm,brcmstb-memc-ddr

      - description: Revision 2.0 controllers

        items:

          - const: brcm,brcmstb-memc-ddr-rev-b.2.0

          - const: brcm,brcmstb-memc-ddr

      - description: Revision 1.x controllers

        items:

          - const: brcm,brcmstb-memc-ddr-rev-b.1.x

          - const: brcm,brcmstb-memc-ddr



  reg:
@@ -46,7 +58,9 @@ additionalProperties: false 
examples:

  - |

    memory-controller@9902000 {

        compatible = "brcm,brcmstb-memc-ddr-rev-c.1.1", "brcm,brcmstb-memc-ddr";

        compatible = "brcm,brcmstb-memc-ddr-rev-c.1.1",

                     "brcm,brcmstb-memc-ddr-rev-b.2.1",

                     "brcm,brcmstb-memc-ddr";

        reg = <0x9902000 0x600>;

        clock-frequency = <2133000000>;

    };