Unverified Commit 0fb32b77 authored by Alessio Belle's avatar Alessio Belle Committed by Matt Coster
Browse files

drm/imagination: Update register defs for newer GPUs 



Update the register define header to a newer version that covers more
recent GPUs, including BXS-4-64.

Signed-off-by: default avatarAlessio Belle <alessio.belle@imgtec.com>
Reviewed-by: default avatarFrank Binns <frank.binns@imgtec.com>
Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-3-eda620c5865f@imgtec.com


Signed-off-by: default avatarMatt Coster <matt.coster@imgtec.com>
parent 86e3f3a6

drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h

+134 −19
Original line number Diff line number Diff line
@@ -827,6 +827,120 @@ 
#define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_CLRMSK 0xFFFFFFFEU

#define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_EN 0x00000001U



/* Register ROGUE_CR_EVENT_CLEAR */

#define ROGUE_CR_EVENT_CLEAR 0x0138U

#define ROGUE_CR_EVENT_CLEAR__ROGUEXE__MASKFULL 0x00000000E01DFFFFULL

#define ROGUE_CR_EVENT_CLEAR__SIGNALS__MASKFULL 0x00000000E007FFFFULL

#define ROGUE_CR_EVENT_CLEAR_MASKFULL 0x00000000FFFFFFFFULL

#define ROGUE_CR_EVENT_CLEAR_TDM_FENCE_FINISHED_SHIFT 31U

#define ROGUE_CR_EVENT_CLEAR_TDM_FENCE_FINISHED_CLRMSK 0x7FFFFFFFU

#define ROGUE_CR_EVENT_CLEAR_TDM_FENCE_FINISHED_EN 0x80000000U

#define ROGUE_CR_EVENT_CLEAR_TDM_BUFFER_STALL_SHIFT 30U

#define ROGUE_CR_EVENT_CLEAR_TDM_BUFFER_STALL_CLRMSK 0xBFFFFFFFU

#define ROGUE_CR_EVENT_CLEAR_TDM_BUFFER_STALL_EN 0x40000000U

#define ROGUE_CR_EVENT_CLEAR_COMPUTE_SIGNAL_FAILURE_SHIFT 29U

#define ROGUE_CR_EVENT_CLEAR_COMPUTE_SIGNAL_FAILURE_CLRMSK 0xDFFFFFFFU

#define ROGUE_CR_EVENT_CLEAR_COMPUTE_SIGNAL_FAILURE_EN 0x20000000U

#define ROGUE_CR_EVENT_CLEAR_DPX_OUT_OF_MEMORY_SHIFT 28U

#define ROGUE_CR_EVENT_CLEAR_DPX_OUT_OF_MEMORY_CLRMSK 0xEFFFFFFFU

#define ROGUE_CR_EVENT_CLEAR_DPX_OUT_OF_MEMORY_EN 0x10000000U

#define ROGUE_CR_EVENT_CLEAR_DPX_MMU_PAGE_FAULT_SHIFT 27U

#define ROGUE_CR_EVENT_CLEAR_DPX_MMU_PAGE_FAULT_CLRMSK 0xF7FFFFFFU

#define ROGUE_CR_EVENT_CLEAR_DPX_MMU_PAGE_FAULT_EN 0x08000000U

#define ROGUE_CR_EVENT_CLEAR_RPM_OUT_OF_MEMORY_SHIFT 26U

#define ROGUE_CR_EVENT_CLEAR_RPM_OUT_OF_MEMORY_CLRMSK 0xFBFFFFFFU

#define ROGUE_CR_EVENT_CLEAR_RPM_OUT_OF_MEMORY_EN 0x04000000U

#define ROGUE_CR_EVENT_CLEAR_FBA_FC3_FINISHED_SHIFT 25U

#define ROGUE_CR_EVENT_CLEAR_FBA_FC3_FINISHED_CLRMSK 0xFDFFFFFFU

#define ROGUE_CR_EVENT_CLEAR_FBA_FC3_FINISHED_EN 0x02000000U

#define ROGUE_CR_EVENT_CLEAR_FBA_FC2_FINISHED_SHIFT 24U

#define ROGUE_CR_EVENT_CLEAR_FBA_FC2_FINISHED_CLRMSK 0xFEFFFFFFU

#define ROGUE_CR_EVENT_CLEAR_FBA_FC2_FINISHED_EN 0x01000000U

#define ROGUE_CR_EVENT_CLEAR_FBA_FC1_FINISHED_SHIFT 23U

#define ROGUE_CR_EVENT_CLEAR_FBA_FC1_FINISHED_CLRMSK 0xFF7FFFFFU

#define ROGUE_CR_EVENT_CLEAR_FBA_FC1_FINISHED_EN 0x00800000U

#define ROGUE_CR_EVENT_CLEAR_FBA_FC0_FINISHED_SHIFT 22U

#define ROGUE_CR_EVENT_CLEAR_FBA_FC0_FINISHED_CLRMSK 0xFFBFFFFFU

#define ROGUE_CR_EVENT_CLEAR_FBA_FC0_FINISHED_EN 0x00400000U

#define ROGUE_CR_EVENT_CLEAR_RDM_FC3_FINISHED_SHIFT 21U

#define ROGUE_CR_EVENT_CLEAR_RDM_FC3_FINISHED_CLRMSK 0xFFDFFFFFU

#define ROGUE_CR_EVENT_CLEAR_RDM_FC3_FINISHED_EN 0x00200000U

#define ROGUE_CR_EVENT_CLEAR_RDM_FC2_FINISHED_SHIFT 20U

#define ROGUE_CR_EVENT_CLEAR_RDM_FC2_FINISHED_CLRMSK 0xFFEFFFFFU

#define ROGUE_CR_EVENT_CLEAR_RDM_FC2_FINISHED_EN 0x00100000U

#define ROGUE_CR_EVENT_CLEAR_SAFETY_SHIFT 20U

#define ROGUE_CR_EVENT_CLEAR_SAFETY_CLRMSK 0xFFEFFFFFU

#define ROGUE_CR_EVENT_CLEAR_SAFETY_EN 0x00100000U

#define ROGUE_CR_EVENT_CLEAR_RDM_FC1_FINISHED_SHIFT 19U

#define ROGUE_CR_EVENT_CLEAR_RDM_FC1_FINISHED_CLRMSK 0xFFF7FFFFU

#define ROGUE_CR_EVENT_CLEAR_RDM_FC1_FINISHED_EN 0x00080000U

#define ROGUE_CR_EVENT_CLEAR_SLAVE_REQ_SHIFT 19U

#define ROGUE_CR_EVENT_CLEAR_SLAVE_REQ_CLRMSK 0xFFF7FFFFU

#define ROGUE_CR_EVENT_CLEAR_SLAVE_REQ_EN 0x00080000U

#define ROGUE_CR_EVENT_CLEAR_RDM_FC0_FINISHED_SHIFT 18U

#define ROGUE_CR_EVENT_CLEAR_RDM_FC0_FINISHED_CLRMSK 0xFFFBFFFFU

#define ROGUE_CR_EVENT_CLEAR_RDM_FC0_FINISHED_EN 0x00040000U

#define ROGUE_CR_EVENT_CLEAR_TDM_CONTEXT_STORE_FINISHED_SHIFT 18U

#define ROGUE_CR_EVENT_CLEAR_TDM_CONTEXT_STORE_FINISHED_CLRMSK 0xFFFBFFFFU

#define ROGUE_CR_EVENT_CLEAR_TDM_CONTEXT_STORE_FINISHED_EN 0x00040000U

#define ROGUE_CR_EVENT_CLEAR_SHG_FINISHED_SHIFT 17U

#define ROGUE_CR_EVENT_CLEAR_SHG_FINISHED_CLRMSK 0xFFFDFFFFU

#define ROGUE_CR_EVENT_CLEAR_SHG_FINISHED_EN 0x00020000U

#define ROGUE_CR_EVENT_CLEAR_SPFILTER_SIGNAL_UPDATE_SHIFT 17U

#define ROGUE_CR_EVENT_CLEAR_SPFILTER_SIGNAL_UPDATE_CLRMSK 0xFFFDFFFFU

#define ROGUE_CR_EVENT_CLEAR_SPFILTER_SIGNAL_UPDATE_EN 0x00020000U

#define ROGUE_CR_EVENT_CLEAR_COMPUTE_BUFFER_STALL_SHIFT 16U

#define ROGUE_CR_EVENT_CLEAR_COMPUTE_BUFFER_STALL_CLRMSK 0xFFFEFFFFU

#define ROGUE_CR_EVENT_CLEAR_COMPUTE_BUFFER_STALL_EN 0x00010000U

#define ROGUE_CR_EVENT_CLEAR_USC_TRIGGER_SHIFT 15U

#define ROGUE_CR_EVENT_CLEAR_USC_TRIGGER_CLRMSK 0xFFFF7FFFU

#define ROGUE_CR_EVENT_CLEAR_USC_TRIGGER_EN 0x00008000U

#define ROGUE_CR_EVENT_CLEAR_ZLS_FINISHED_SHIFT 14U

#define ROGUE_CR_EVENT_CLEAR_ZLS_FINISHED_CLRMSK 0xFFFFBFFFU

#define ROGUE_CR_EVENT_CLEAR_ZLS_FINISHED_EN 0x00004000U

#define ROGUE_CR_EVENT_CLEAR_GPIO_ACK_SHIFT 13U

#define ROGUE_CR_EVENT_CLEAR_GPIO_ACK_CLRMSK 0xFFFFDFFFU

#define ROGUE_CR_EVENT_CLEAR_GPIO_ACK_EN 0x00002000U

#define ROGUE_CR_EVENT_CLEAR_GPIO_REQ_SHIFT 12U

#define ROGUE_CR_EVENT_CLEAR_GPIO_REQ_CLRMSK 0xFFFFEFFFU

#define ROGUE_CR_EVENT_CLEAR_GPIO_REQ_EN 0x00001000U

#define ROGUE_CR_EVENT_CLEAR_POWER_ABORT_SHIFT 11U

#define ROGUE_CR_EVENT_CLEAR_POWER_ABORT_CLRMSK 0xFFFFF7FFU

#define ROGUE_CR_EVENT_CLEAR_POWER_ABORT_EN 0x00000800U

#define ROGUE_CR_EVENT_CLEAR_POWER_COMPLETE_SHIFT 10U

#define ROGUE_CR_EVENT_CLEAR_POWER_COMPLETE_CLRMSK 0xFFFFFBFFU

#define ROGUE_CR_EVENT_CLEAR_POWER_COMPLETE_EN 0x00000400U

#define ROGUE_CR_EVENT_CLEAR_MMU_PAGE_FAULT_SHIFT 9U

#define ROGUE_CR_EVENT_CLEAR_MMU_PAGE_FAULT_CLRMSK 0xFFFFFDFFU

#define ROGUE_CR_EVENT_CLEAR_MMU_PAGE_FAULT_EN 0x00000200U

#define ROGUE_CR_EVENT_CLEAR_PM_3D_MEM_FREE_SHIFT 8U

#define ROGUE_CR_EVENT_CLEAR_PM_3D_MEM_FREE_CLRMSK 0xFFFFFEFFU

#define ROGUE_CR_EVENT_CLEAR_PM_3D_MEM_FREE_EN 0x00000100U

#define ROGUE_CR_EVENT_CLEAR_PM_OUT_OF_MEMORY_SHIFT 7U

#define ROGUE_CR_EVENT_CLEAR_PM_OUT_OF_MEMORY_CLRMSK 0xFFFFFF7FU

#define ROGUE_CR_EVENT_CLEAR_PM_OUT_OF_MEMORY_EN 0x00000080U

#define ROGUE_CR_EVENT_CLEAR_TA_TERMINATE_SHIFT 6U

#define ROGUE_CR_EVENT_CLEAR_TA_TERMINATE_CLRMSK 0xFFFFFFBFU

#define ROGUE_CR_EVENT_CLEAR_TA_TERMINATE_EN 0x00000040U

#define ROGUE_CR_EVENT_CLEAR_TA_FINISHED_SHIFT 5U

#define ROGUE_CR_EVENT_CLEAR_TA_FINISHED_CLRMSK 0xFFFFFFDFU

#define ROGUE_CR_EVENT_CLEAR_TA_FINISHED_EN 0x00000020U

#define ROGUE_CR_EVENT_CLEAR_ISP_END_MACROTILE_SHIFT 4U

#define ROGUE_CR_EVENT_CLEAR_ISP_END_MACROTILE_CLRMSK 0xFFFFFFEFU

#define ROGUE_CR_EVENT_CLEAR_ISP_END_MACROTILE_EN 0x00000010U

#define ROGUE_CR_EVENT_CLEAR_PIXELBE_END_RENDER_SHIFT 3U

#define ROGUE_CR_EVENT_CLEAR_PIXELBE_END_RENDER_CLRMSK 0xFFFFFFF7U

#define ROGUE_CR_EVENT_CLEAR_PIXELBE_END_RENDER_EN 0x00000008U

#define ROGUE_CR_EVENT_CLEAR_COMPUTE_FINISHED_SHIFT 2U

#define ROGUE_CR_EVENT_CLEAR_COMPUTE_FINISHED_CLRMSK 0xFFFFFFFBU

#define ROGUE_CR_EVENT_CLEAR_COMPUTE_FINISHED_EN 0x00000004U

#define ROGUE_CR_EVENT_CLEAR_KERNEL_FINISHED_SHIFT 1U

#define ROGUE_CR_EVENT_CLEAR_KERNEL_FINISHED_CLRMSK 0xFFFFFFFDU

#define ROGUE_CR_EVENT_CLEAR_KERNEL_FINISHED_EN 0x00000002U

#define ROGUE_CR_EVENT_CLEAR_TLA_COMPLETE_SHIFT 0U

#define ROGUE_CR_EVENT_CLEAR_TLA_COMPLETE_CLRMSK 0xFFFFFFFEU

#define ROGUE_CR_EVENT_CLEAR_TLA_COMPLETE_EN 0x00000001U



/* Register ROGUE_CR_TIMER */

#define ROGUE_CR_TIMER 0x0160U

#define ROGUE_CR_TIMER_MASKFULL 0x8000FFFFFFFFFFFFULL
@@ -6031,25 +6145,6 @@ 
#define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_GPU_ENABLE_SHIFT 0U

#define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_GPU_ENABLE_CLRMSK 0xFFFFFF00U



/* Register ROGUE_CR_ECC_RAM_ERR_INJ */

#define ROGUE_CR_ECC_RAM_ERR_INJ 0xF340U

#define ROGUE_CR_ECC_RAM_ERR_INJ_MASKFULL 0x000000000000001FULL

#define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_SHIFT 4U

#define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_CLRMSK 0xFFFFFFEFU

#define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_EN 0x00000010U

#define ROGUE_CR_ECC_RAM_ERR_INJ_USC_SHIFT 3U

#define ROGUE_CR_ECC_RAM_ERR_INJ_USC_CLRMSK 0xFFFFFFF7U

#define ROGUE_CR_ECC_RAM_ERR_INJ_USC_EN 0x00000008U

#define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_SHIFT 2U

#define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_CLRMSK 0xFFFFFFFBU

#define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_EN 0x00000004U

#define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_SHIFT 1U

#define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_CLRMSK 0xFFFFFFFDU

#define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_EN 0x00000002U

#define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_SHIFT 0U

#define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_CLRMSK 0xFFFFFFFEU

#define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_EN 0x00000001U



/* Register ROGUE_CR_ECC_RAM_INIT_KICK */

#define ROGUE_CR_ECC_RAM_INIT_KICK 0xF348U

#define ROGUE_CR_ECC_RAM_INIT_KICK_MASKFULL 0x000000000000001FULL
@@ -6163,6 +6258,26 @@ 
#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_CLRMSK 0xFFFFFFFEU

#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_EN 0x00000001U



/* Register ROGUE_CR_FAULT_FW_STATUS */

#define ROGUE_CR_FAULT_FW_STATUS 0xF3B0U

#define ROGUE_CR_FAULT_FW_STATUS_MASKFULL 0x0000000000010001ULL

#define ROGUE_CR_FAULT_FW_STATUS_CPU_CORRECT_SHIFT 16U

#define ROGUE_CR_FAULT_FW_STATUS_CPU_CORRECT_CLRMSK 0xFFFEFFFFU

#define ROGUE_CR_FAULT_FW_STATUS_CPU_CORRECT_EN 0x00010000U

#define ROGUE_CR_FAULT_FW_STATUS_CPU_DETECT_SHIFT 0U

#define ROGUE_CR_FAULT_FW_STATUS_CPU_DETECT_CLRMSK 0xFFFFFFFEU

#define ROGUE_CR_FAULT_FW_STATUS_CPU_DETECT_EN 0x00000001U



/* Register ROGUE_CR_FAULT_FW_CLEAR */

#define ROGUE_CR_FAULT_FW_CLEAR 0xF3B8U

#define ROGUE_CR_FAULT_FW_CLEAR_MASKFULL 0x0000000000010001ULL

#define ROGUE_CR_FAULT_FW_CLEAR_CPU_CORRECT_SHIFT 16U

#define ROGUE_CR_FAULT_FW_CLEAR_CPU_CORRECT_CLRMSK 0xFFFEFFFFU

#define ROGUE_CR_FAULT_FW_CLEAR_CPU_CORRECT_EN 0x00010000U

#define ROGUE_CR_FAULT_FW_CLEAR_CPU_DETECT_SHIFT 0U

#define ROGUE_CR_FAULT_FW_CLEAR_CPU_DETECT_CLRMSK 0xFFFFFFFEU

#define ROGUE_CR_FAULT_FW_CLEAR_CPU_DETECT_EN 0x00000001U



/* Register ROGUE_CR_MTS_SAFETY_EVENT_ENABLE */

#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE 0xF3D8U

#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__MASKFULL 0x000000000000007FULL