Loading arch/sh/kernel/early_printk.c +13 −11 Original line number Diff line number Diff line Loading @@ -141,6 +141,7 @@ static void scif_sercon_init(char *s) */ static void scif_sercon_init(char *s) { struct uart_port *port = &scif_port; unsigned baud = DEFAULT_BAUD; char *e; Loading @@ -160,19 +161,20 @@ static void scif_sercon_init(char *s) baud = DEFAULT_BAUD; } ctrl_outw(0, scif_port.mapbase + 8); ctrl_outw(0, scif_port.mapbase); sci_out(port, SCSCR, 0); /* TE=0, RE=0 */ sci_out(port, SCSMR, 0); /* Set baud rate */ ctrl_outb((CONFIG_SH_PCLK_FREQ + 16 * baud) / (32 * baud) - 1, scif_port.mapbase + 4); ctrl_outw(12, scif_port.mapbase + 24); ctrl_outw(8, scif_port.mapbase + 24); ctrl_outw(0, scif_port.mapbase + 32); ctrl_outw(0x60, scif_port.mapbase + 16); ctrl_outw(0, scif_port.mapbase + 36); ctrl_outw(0x30, scif_port.mapbase + 8); sci_out(port, SCBRR, (CONFIG_SH_PCLK_FREQ + 16 * baud) / (32 * baud) - 1); sci_out(port, SCFCR, 12); sci_out(port, SCFCR, 8); sci_out(port, SCSPTR, 0); sci_out(port, SCxSR, 0x60); sci_out(port, SCLSR, 0); sci_out(port, SCSCR, 0x30); /* TE=1, RE=1 */ } #endif /* defined(CONFIG_CPU_SUBTYPE_SH7720) */ #endif /* !defined(CONFIG_SH_STANDARD_BIOS) */ Loading Loading
arch/sh/kernel/early_printk.c +13 −11 Original line number Diff line number Diff line Loading @@ -141,6 +141,7 @@ static void scif_sercon_init(char *s) */ static void scif_sercon_init(char *s) { struct uart_port *port = &scif_port; unsigned baud = DEFAULT_BAUD; char *e; Loading @@ -160,19 +161,20 @@ static void scif_sercon_init(char *s) baud = DEFAULT_BAUD; } ctrl_outw(0, scif_port.mapbase + 8); ctrl_outw(0, scif_port.mapbase); sci_out(port, SCSCR, 0); /* TE=0, RE=0 */ sci_out(port, SCSMR, 0); /* Set baud rate */ ctrl_outb((CONFIG_SH_PCLK_FREQ + 16 * baud) / (32 * baud) - 1, scif_port.mapbase + 4); ctrl_outw(12, scif_port.mapbase + 24); ctrl_outw(8, scif_port.mapbase + 24); ctrl_outw(0, scif_port.mapbase + 32); ctrl_outw(0x60, scif_port.mapbase + 16); ctrl_outw(0, scif_port.mapbase + 36); ctrl_outw(0x30, scif_port.mapbase + 8); sci_out(port, SCBRR, (CONFIG_SH_PCLK_FREQ + 16 * baud) / (32 * baud) - 1); sci_out(port, SCFCR, 12); sci_out(port, SCFCR, 8); sci_out(port, SCSPTR, 0); sci_out(port, SCxSR, 0x60); sci_out(port, SCLSR, 0); sci_out(port, SCSCR, 0x30); /* TE=1, RE=1 */ } #endif /* defined(CONFIG_CPU_SUBTYPE_SH7720) */ #endif /* !defined(CONFIG_SH_STANDARD_BIOS) */ Loading