Unverified Commit 0fc42d26 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'v7.1-rockchip-clk1' of... 

Merge tag 'v7.1-rockchip-clk1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stuebner:

 - Clock driver for the Rockchip RV1103B SoC

For whatever reason that SoC only got a B addition to the name,
but major changes internally - likely it is pin compatible with
the non-b-variant. Other change is actually exporting PCIe
pipe-clocks that were already in the binding.

* tag 'v7.1-rockchip-clk1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: rk3568: Add PCIe pipe clock gates
  clk: rockchip: Add clock controller for the RV1103B
  dt-bindings: clock: rockchip: Add RV1103B CRU support
parents c3692998 41b1a676

Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml

+1 −0
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@@ -17,6 +17,7 @@ description: 
properties:

  compatible:

    enum:

      - rockchip,rv1103b-cru

      - rockchip,rv1126b-cru



  reg:

drivers/clk/rockchip/Kconfig

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@@ -16,6 +16,13 @@ config CLK_PX30 
	help

	  Build the driver for PX30 Clock Driver.



config CLK_RV1103B

	bool "Rockchip RV1103B clock controller support"

	depends on ARM || COMPILE_TEST

	default y

	help

	  Build the driver for RV1103B Clock Driver.



config CLK_RV110X

	bool "Rockchip RV110x clock controller support"

	depends on ARM || COMPILE_TEST

drivers/clk/rockchip/Makefile

+1 −0
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@@ -18,6 +18,7 @@ clk-rockchip-y += gate-link.o 
clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o



obj-$(CONFIG_CLK_PX30)          += clk-px30.o

obj-$(CONFIG_CLK_RV1103B)	+= clk-rv1103b.o

obj-$(CONFIG_CLK_RV110X)        += clk-rv1108.o

obj-$(CONFIG_CLK_RV1126)        += clk-rv1126.o

obj-$(CONFIG_CLK_RV1126B)	+= clk-rv1126b.o rst-rv1126b.o

drivers/clk/rockchip/clk-rk3568.c

+6 −0
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@@ -827,6 +827,8 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { 
			RK3568_CLKGATE_CON(12), 3, GFLAGS),

	GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0,

			RK3568_CLKGATE_CON(12), 4, GFLAGS),

	GATE(CLK_PCIE20_PIPE_DFT, "clk_pcie20_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED,

			RK3568_CLKGATE_CON(12), 5, GFLAGS),

	GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0,

			RK3568_CLKGATE_CON(12), 8, GFLAGS),

	GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0,
@@ -837,6 +839,8 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { 
			RK3568_CLKGATE_CON(12), 11, GFLAGS),

	GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0,

			RK3568_CLKGATE_CON(12), 12, GFLAGS),

	GATE(CLK_PCIE30X1_PIPE_DFT, "clk_pcie30x1_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED,

			RK3568_CLKGATE_CON(12), 13, GFLAGS),

	GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0,

			RK3568_CLKGATE_CON(13), 0, GFLAGS),

	GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0,
@@ -847,6 +851,8 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { 
			RK3568_CLKGATE_CON(13), 3, GFLAGS),

	GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0,

			RK3568_CLKGATE_CON(13), 4, GFLAGS),

	GATE(CLK_PCIE30X2_PIPE_DFT, "clk_pcie30x2_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED,

			RK3568_CLKGATE_CON(13), 5, GFLAGS),

	GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0,

			RK3568_CLKGATE_CON(11), 0, GFLAGS),

	GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0,

drivers/clk/rockchip/clk-rv1103b.c

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