Commit 0fd76865 authored by Joey Gouly's avatar Joey Gouly Committed by Marc Zyngier
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KVM: arm64: Add nPIR{E0}_EL1 to HFG traps 



nPIR_EL1 and nPIREO_EL1 are part of the 'reverse polarity' set of bits, set
them so that we disable the traps for a guest. Unfortunately, these bits
are not yet described in the ARM ARM, but only live in the XML description.

Also add them to the NV FGT forwarding infrastructure.

Signed-off-by: default avatarJoey Gouly <joey.gouly@arm.com>
Fixes: e930694e ("KVM: arm64: Restructure FGT register switching")
Cc: Oliver Upton <oliver.upton@linux.dev>
[maz: add entries to the NV FGT array, commit message update]
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20231012123459.2820835-2-joey.gouly@arm.com
parent 60197a46

arch/arm64/include/asm/kvm_arm.h

+2 −2
Original line number Diff line number Diff line
@@ -344,14 +344,14 @@ 
 */

#define __HFGRTR_EL2_RES0	(GENMASK(63, 56) | GENMASK(53, 51))

#define __HFGRTR_EL2_MASK	GENMASK(49, 0)

#define __HFGRTR_EL2_nMASK	(GENMASK(55, 54) | BIT(50))

#define __HFGRTR_EL2_nMASK	(GENMASK(58, 57) | GENMASK(55, 54) | BIT(50))



#define __HFGWTR_EL2_RES0	(GENMASK(63, 56) | GENMASK(53, 51) |	\

				 BIT(46) | BIT(42) | BIT(40) | BIT(28) | \

				 GENMASK(26, 25) | BIT(21) | BIT(18) |	\

				 GENMASK(15, 14) | GENMASK(10, 9) | BIT(2))

#define __HFGWTR_EL2_MASK	GENMASK(49, 0)

#define __HFGWTR_EL2_nMASK	(GENMASK(55, 54) | BIT(50))

#define __HFGWTR_EL2_nMASK	(GENMASK(58, 57) | GENMASK(55, 54) | BIT(50))



#define __HFGITR_EL2_RES0	GENMASK(63, 57)

#define __HFGITR_EL2_MASK	GENMASK(54, 0)

arch/arm64/kvm/emulate-nested.c

+2 −0
Original line number Diff line number Diff line
@@ -977,6 +977,8 @@ enum fg_filter_id { 


static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = {

	/* HFGRTR_EL2, HFGWTR_EL2 */

	SR_FGT(SYS_PIR_EL1,		HFGxTR, nPIR_EL1, 0),

	SR_FGT(SYS_PIRE0_EL1,		HFGxTR, nPIRE0_EL1, 0),

	SR_FGT(SYS_TPIDR2_EL0,		HFGxTR, nTPIDR2_EL0, 0),

	SR_FGT(SYS_SMPRI_EL1,		HFGxTR, nSMPRI_EL1, 0),

	SR_FGT(SYS_ACCDATA_EL1,		HFGxTR, nACCDATA_EL1, 0),