Commit 0fe41a87 authored by Marc Kleine-Budde's avatar Marc Kleine-Budde
Browse files

Merge patch series "can: esd_402_pci: Do cleanup; Add one-shot mode" 

Stefan Mätje <stefan.maetje@esd.eu> says:

The goal of this patch series is to do some cleanup
and also add the support for the one-shot mode before
the next patch introduces CAN-FD support for this
driver.

Link: https://lore.kernel.org/all/20240717214409.3934333-1-stefan.maetje@esd.eu


Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
parents 72e5f5a9 c20ff3e0

drivers/net/can/esd/esd_402_pci-core.c

+3 −2
Original line number Diff line number Diff line
@@ -369,12 +369,13 @@ static int pci402_init_cores(struct pci_dev *pdev) 
		SET_NETDEV_DEV(netdev, &pdev->dev);



		priv = netdev_priv(netdev);

		priv->can.clock.freq = card->ov.core_frequency;

		priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |

			CAN_CTRLMODE_LISTENONLY |

			CAN_CTRLMODE_BERR_REPORTING |

			CAN_CTRLMODE_CC_LEN8_DLC;



		priv->can.clock.freq = card->ov.core_frequency;

		if (card->ov.features & ACC_OV_REG_FEAT_MASK_DAR)

			priv->can.ctrlmode_supported |= CAN_CTRLMODE_ONE_SHOT;

		if (card->ov.features & ACC_OV_REG_FEAT_MASK_CANFD)

			priv->can.bittiming_const = &pci402_bittiming_const_canfd;

		else

drivers/net/can/esd/esdacc.c

+30 −25
Original line number Diff line number Diff line
@@ -17,6 +17,9 @@ 
/* esdACC DLC register layout */

#define ACC_DLC_DLC_MASK GENMASK(3, 0)

#define ACC_DLC_RTR_FLAG BIT(4)

#define ACC_DLC_SSTX_FLAG BIT(24)	/* Single Shot TX */



/* esdACC DLC in struct acc_bmmsg_rxtxdone::acc_dlc.len only! */

#define ACC_DLC_TXD_FLAG BIT(5)



/* ecc value of esdACC equals SJA1000's ECC register */
@@ -43,8 +46,8 @@ 


static void acc_resetmode_enter(struct acc_core *core)

{

	acc_set_bits(core, ACC_CORE_OF_CTRL_MODE,

		     ACC_REG_CONTROL_MASK_MODE_RESETMODE);

	acc_set_bits(core, ACC_CORE_OF_CTRL,

		     ACC_REG_CTRL_MASK_RESETMODE);



	/* Read back reset mode bit to flush PCI write posting */

	acc_resetmode_entered(core);
@@ -52,14 +55,14 @@ static void acc_resetmode_enter(struct acc_core *core) 


static void acc_resetmode_leave(struct acc_core *core)

{

	acc_clear_bits(core, ACC_CORE_OF_CTRL_MODE,

		       ACC_REG_CONTROL_MASK_MODE_RESETMODE);

	acc_clear_bits(core, ACC_CORE_OF_CTRL,

		       ACC_REG_CTRL_MASK_RESETMODE);



	/* Read back reset mode bit to flush PCI write posting */

	acc_resetmode_entered(core);

}



static void acc_txq_put(struct acc_core *core, u32 acc_id, u8 acc_dlc,

static void acc_txq_put(struct acc_core *core, u32 acc_id, u32 acc_dlc,

			const void *data)

{

	acc_write32_noswap(core, ACC_CORE_OF_TXFIFO_DATA_1,
@@ -172,7 +175,7 @@ int acc_open(struct net_device *netdev) 
	struct acc_net_priv *priv = netdev_priv(netdev);

	struct acc_core *core = priv->core;

	u32 tx_fifo_status;

	u32 ctrl_mode;

	u32 ctrl;

	int err;



	/* Retry to enter RESET mode if out of sync. */
@@ -187,19 +190,19 @@ int acc_open(struct net_device *netdev) 
	if (err)

		return err;



	ctrl_mode = ACC_REG_CONTROL_MASK_IE_RXTX |

			ACC_REG_CONTROL_MASK_IE_TXERROR |

			ACC_REG_CONTROL_MASK_IE_ERRWARN |

			ACC_REG_CONTROL_MASK_IE_OVERRUN |

			ACC_REG_CONTROL_MASK_IE_ERRPASS;

	ctrl = ACC_REG_CTRL_MASK_IE_RXTX |

		ACC_REG_CTRL_MASK_IE_TXERROR |

		ACC_REG_CTRL_MASK_IE_ERRWARN |

		ACC_REG_CTRL_MASK_IE_OVERRUN |

		ACC_REG_CTRL_MASK_IE_ERRPASS;



	if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)

		ctrl_mode |= ACC_REG_CONTROL_MASK_IE_BUSERR;

		ctrl |= ACC_REG_CTRL_MASK_IE_BUSERR;



	if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)

		ctrl_mode |= ACC_REG_CONTROL_MASK_MODE_LOM;

		ctrl |= ACC_REG_CTRL_MASK_LOM;



	acc_set_bits(core, ACC_CORE_OF_CTRL_MODE, ctrl_mode);

	acc_set_bits(core, ACC_CORE_OF_CTRL, ctrl);



	acc_resetmode_leave(core);

	priv->can.state = CAN_STATE_ERROR_ACTIVE;
@@ -218,13 +221,13 @@ int acc_close(struct net_device *netdev) 
	struct acc_net_priv *priv = netdev_priv(netdev);

	struct acc_core *core = priv->core;



	acc_clear_bits(core, ACC_CORE_OF_CTRL_MODE,

		       ACC_REG_CONTROL_MASK_IE_RXTX |

		       ACC_REG_CONTROL_MASK_IE_TXERROR |

		       ACC_REG_CONTROL_MASK_IE_ERRWARN |

		       ACC_REG_CONTROL_MASK_IE_OVERRUN |

		       ACC_REG_CONTROL_MASK_IE_ERRPASS |

		       ACC_REG_CONTROL_MASK_IE_BUSERR);

	acc_clear_bits(core, ACC_CORE_OF_CTRL,

		       ACC_REG_CTRL_MASK_IE_RXTX |

		       ACC_REG_CTRL_MASK_IE_TXERROR |

		       ACC_REG_CTRL_MASK_IE_ERRWARN |

		       ACC_REG_CTRL_MASK_IE_OVERRUN |

		       ACC_REG_CTRL_MASK_IE_ERRPASS |

		       ACC_REG_CTRL_MASK_IE_BUSERR);



	netif_stop_queue(netdev);

	acc_resetmode_enter(core);
@@ -233,9 +236,9 @@ int acc_close(struct net_device *netdev) 
	/* Mark pending TX requests to be aborted after controller restart. */

	acc_write32(core, ACC_CORE_OF_TX_ABORT_MASK, 0xffff);



	/* ACC_REG_CONTROL_MASK_MODE_LOM is only accessible in RESET mode */

	acc_clear_bits(core, ACC_CORE_OF_CTRL_MODE,

		       ACC_REG_CONTROL_MASK_MODE_LOM);

	/* ACC_REG_CTRL_MASK_LOM is only accessible in RESET mode */

	acc_clear_bits(core, ACC_CORE_OF_CTRL,

		       ACC_REG_CTRL_MASK_LOM);



	close_candev(netdev);

	return 0;
@@ -249,7 +252,7 @@ netdev_tx_t acc_start_xmit(struct sk_buff *skb, struct net_device *netdev) 
	u8 tx_fifo_head = core->tx_fifo_head;

	int fifo_usage;

	u32 acc_id;

	u8 acc_dlc;

	u32 acc_dlc;



	if (can_dropped_invalid_skb(netdev, skb))

		return NETDEV_TX_OK;
@@ -274,6 +277,8 @@ netdev_tx_t acc_start_xmit(struct sk_buff *skb, struct net_device *netdev) 
	acc_dlc = can_get_cc_dlc(cf, priv->can.ctrlmode);

	if (cf->can_id & CAN_RTR_FLAG)

		acc_dlc |= ACC_DLC_RTR_FLAG;

	if (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)

		acc_dlc |= ACC_DLC_SSTX_FLAG;



	if (cf->can_id & CAN_EFF_FLAG) {

		acc_id = cf->can_id & CAN_EFF_MASK;

drivers/net/can/esd/esdacc.h

+20 −18
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ 
 */

#define ACC_OV_REG_FEAT_MASK_CANFD BIT(27 - 16)

#define ACC_OV_REG_FEAT_MASK_NEW_PSC BIT(28 - 16)

#define ACC_OV_REG_FEAT_MASK_DAR BIT(30 - 16)



#define ACC_OV_REG_MODE_MASK_ENDIAN_LITTLE BIT(0)

#define ACC_OV_REG_MODE_MASK_BM_ENABLE BIT(1)
@@ -50,7 +51,7 @@ 
#define ACC_OV_REG_MODE_MASK_FPGA_RESET BIT(31)



/* esdACC CAN Core Module */

#define ACC_CORE_OF_CTRL_MODE 0x0000

#define ACC_CORE_OF_CTRL 0x0000

#define ACC_CORE_OF_STATUS_IRQ 0x0008

#define ACC_CORE_OF_BRP	0x000c

#define ACC_CORE_OF_BTR	0x0010
@@ -66,21 +67,22 @@ 
#define ACC_CORE_OF_TXFIFO_DATA_0 0x00c8

#define ACC_CORE_OF_TXFIFO_DATA_1 0x00cc



#define ACC_REG_CONTROL_MASK_MODE_RESETMODE BIT(0)

#define ACC_REG_CONTROL_MASK_MODE_LOM BIT(1)

#define ACC_REG_CONTROL_MASK_MODE_STM BIT(2)

#define ACC_REG_CONTROL_MASK_MODE_TRANSEN BIT(5)

#define ACC_REG_CONTROL_MASK_MODE_TS BIT(6)

#define ACC_REG_CONTROL_MASK_MODE_SCHEDULE BIT(7)



#define ACC_REG_CONTROL_MASK_IE_RXTX BIT(8)

#define ACC_REG_CONTROL_MASK_IE_TXERROR BIT(9)

#define ACC_REG_CONTROL_MASK_IE_ERRWARN BIT(10)

#define ACC_REG_CONTROL_MASK_IE_OVERRUN BIT(11)

#define ACC_REG_CONTROL_MASK_IE_TSI BIT(12)

#define ACC_REG_CONTROL_MASK_IE_ERRPASS BIT(13)

#define ACC_REG_CONTROL_MASK_IE_ALI BIT(14)

#define ACC_REG_CONTROL_MASK_IE_BUSERR BIT(15)

/* CTRL register layout */

#define ACC_REG_CTRL_MASK_RESETMODE BIT(0)

#define ACC_REG_CTRL_MASK_LOM BIT(1)

#define ACC_REG_CTRL_MASK_STM BIT(2)

#define ACC_REG_CTRL_MASK_TRANSEN BIT(5)

#define ACC_REG_CTRL_MASK_TS BIT(6)

#define ACC_REG_CTRL_MASK_SCHEDULE BIT(7)



#define ACC_REG_CTRL_MASK_IE_RXTX BIT(8)

#define ACC_REG_CTRL_MASK_IE_TXERROR BIT(9)

#define ACC_REG_CTRL_MASK_IE_ERRWARN BIT(10)

#define ACC_REG_CTRL_MASK_IE_OVERRUN BIT(11)

#define ACC_REG_CTRL_MASK_IE_TSI BIT(12)

#define ACC_REG_CTRL_MASK_IE_ERRPASS BIT(13)

#define ACC_REG_CTRL_MASK_IE_ALI BIT(14)

#define ACC_REG_CTRL_MASK_IE_BUSERR BIT(15)



/* BRP and BTR register layout for CAN-Classic version */

#define ACC_REG_BRP_CL_MASK_BRP GENMASK(8, 0)
@@ -300,9 +302,9 @@ static inline void acc_clear_bits(struct acc_core *core, 


static inline int acc_resetmode_entered(struct acc_core *core)

{

	u32 ctrl = acc_read32(core, ACC_CORE_OF_CTRL_MODE);

	u32 ctrl = acc_read32(core, ACC_CORE_OF_CTRL);



	return (ctrl & ACC_REG_CONTROL_MASK_MODE_RESETMODE) != 0;

	return (ctrl & ACC_REG_CTRL_MASK_RESETMODE) != 0;

}



static inline u32 acc_ov_read32(struct acc_ov *ov, unsigned short offs)