Commit 0fed2905 authored by Michael Chan's avatar Michael Chan Committed by Jakub Kicinski
Browse files

bnxt_en: Refactor completion ring allocation logic for P5_PLUS chips 



Add a new bnxt_hwrm_cp_ring_alloc_p5() function to handle allocating
one completion ring on P5_PLUS chips.  This simplifies the existing code
and will be useful later in the series.

Reviewed-by: default avatarAjit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: default avatarMichal Swiatkowski <michal.swiatkowski@linux.intel.com>
Signed-off-by: default avatarMichael Chan <michael.chan@broadcom.com>
Link: https://patch.msgid.link/20250213011240.1640031-3-michael.chan@broadcom.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent ebdf7fe4

drivers/net/ethernet/broadcom/bnxt/bnxt.c

+21 −23
Original line number Diff line number Diff line
@@ -7199,6 +7199,25 @@ static int bnxt_hwrm_rx_agg_ring_alloc(struct bnxt *bp, 
	return 0;

}



static int bnxt_hwrm_cp_ring_alloc_p5(struct bnxt *bp,

				      struct bnxt_cp_ring_info *cpr)

{

	const u32 type = HWRM_RING_ALLOC_CMPL;

	struct bnxt_napi *bnapi = cpr->bnapi;

	struct bnxt_ring_struct *ring;

	u32 map_idx = bnapi->index;

	int rc;



	ring = &cpr->cp_ring_struct;

	ring->handle = BNXT_SET_NQ_HDL(cpr);

	rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);

	if (rc)

		return rc;

	bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);

	bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);

	return 0;

}



static int bnxt_hwrm_ring_alloc(struct bnxt *bp)

{

	bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS);
@@ -7242,19 +7261,9 @@ static int bnxt_hwrm_ring_alloc(struct bnxt *bp) 
		u32 map_idx;



		if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {

			struct bnxt_cp_ring_info *cpr2 = txr->tx_cpr;

			struct bnxt_napi *bnapi = txr->bnapi;

			u32 type2 = HWRM_RING_ALLOC_CMPL;



			ring = &cpr2->cp_ring_struct;

			ring->handle = BNXT_SET_NQ_HDL(cpr2);

			map_idx = bnapi->index;

			rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);

			rc = bnxt_hwrm_cp_ring_alloc_p5(bp, txr->tx_cpr);

			if (rc)

				goto err_out;

			bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,

				    ring->fw_ring_id);

			bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);

		}

		ring = &txr->tx_ring_struct;

		map_idx = i;
@@ -7274,20 +7283,9 @@ static int bnxt_hwrm_ring_alloc(struct bnxt *bp) 
		if (!agg_rings)

			bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);

		if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {

			struct bnxt_cp_ring_info *cpr2 = rxr->rx_cpr;

			struct bnxt_napi *bnapi = rxr->bnapi;

			u32 type2 = HWRM_RING_ALLOC_CMPL;

			struct bnxt_ring_struct *ring;

			u32 map_idx = bnapi->index;



			ring = &cpr2->cp_ring_struct;

			ring->handle = BNXT_SET_NQ_HDL(cpr2);

			rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);

			rc = bnxt_hwrm_cp_ring_alloc_p5(bp, rxr->rx_cpr);

			if (rc)

				goto err_out;

			bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,

				    ring->fw_ring_id);

			bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);

		}

	}