Loading drivers/pci/controller/pcie-rcar-host.c +2 −2 Original line number Diff line number Diff line Loading @@ -796,8 +796,8 @@ static int rcar_pcie_enable_msi(struct rcar_pcie_host *host) rcar_pci_write_reg(pcie, 0, PCIEMSIIER); /* * Setup MSI data target using RC base address address, which * is guaranteed to be in the low 32bit range on any R-Car HW. * Setup MSI data target using RC base address, which is guaranteed * to be in the low 32bit range on any R-Car HW. */ rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR); rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR); Loading drivers/pci/pcie/aer.c +9 −6 Original line number Diff line number Diff line Loading @@ -180,7 +180,8 @@ static int disable_ecrc_checking(struct pci_dev *dev) } /** * pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based on global policy * pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based * on global policy * @dev: the PCI device */ void pcie_set_ecrc_checking(struct pci_dev *dev) Loading Loading @@ -1148,11 +1149,13 @@ static void aer_recover_work_func(struct work_struct *work) continue; } pci_print_aer(pdev, entry.severity, entry.regs); /* * Memory for aer_capability_regs(entry.regs) is being allocated from the * ghes_estatus_pool to protect it from overwriting when multiple sections * are present in the error status. Thus free the same after processing * the data. * Memory for aer_capability_regs(entry.regs) is being * allocated from the ghes_estatus_pool to protect it from * overwriting when multiple sections are present in the * error status. Thus free the same after processing the * data. */ ghes_estatus_pool_region_free((unsigned long)entry.regs, sizeof(struct aer_capability_regs)); Loading Loading
drivers/pci/controller/pcie-rcar-host.c +2 −2 Original line number Diff line number Diff line Loading @@ -796,8 +796,8 @@ static int rcar_pcie_enable_msi(struct rcar_pcie_host *host) rcar_pci_write_reg(pcie, 0, PCIEMSIIER); /* * Setup MSI data target using RC base address address, which * is guaranteed to be in the low 32bit range on any R-Car HW. * Setup MSI data target using RC base address, which is guaranteed * to be in the low 32bit range on any R-Car HW. */ rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR); rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR); Loading
drivers/pci/pcie/aer.c +9 −6 Original line number Diff line number Diff line Loading @@ -180,7 +180,8 @@ static int disable_ecrc_checking(struct pci_dev *dev) } /** * pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based on global policy * pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based * on global policy * @dev: the PCI device */ void pcie_set_ecrc_checking(struct pci_dev *dev) Loading Loading @@ -1148,11 +1149,13 @@ static void aer_recover_work_func(struct work_struct *work) continue; } pci_print_aer(pdev, entry.severity, entry.regs); /* * Memory for aer_capability_regs(entry.regs) is being allocated from the * ghes_estatus_pool to protect it from overwriting when multiple sections * are present in the error status. Thus free the same after processing * the data. * Memory for aer_capability_regs(entry.regs) is being * allocated from the ghes_estatus_pool to protect it from * overwriting when multiple sections are present in the * error status. Thus free the same after processing the * data. */ ghes_estatus_pool_region_free((unsigned long)entry.regs, sizeof(struct aer_capability_regs)); Loading