Commit 102534b0 authored by Josh Poimboeuf's avatar Josh Poimboeuf Committed by Alex Deucher
Browse files

drm/radeon: refactor SI tiling table initialization 



Simplify the control flow of si_tiling_mode_table_init() similar to how
it was done in gfx_v7_0.c and gfx_v8_0.c.

Signed-off-by: default avatarJosh Poimboeuf <jpoimboe@redhat.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f0e201f2

drivers/gpu/drm/radeon/si.c

+439 −486
Original line number Diff line number Diff line
@@ -2442,8 +2442,10 @@ void dce6_bandwidth_update(struct radeon_device *rdev) 
 */

static void si_tiling_mode_table_init(struct radeon_device *rdev)

{

	const u32 num_tile_mode_states = 32;

	u32 reg_offset, gb_tile_moden, split_equal_to_row_size;

	u32 *tile = rdev->config.si.tile_mode_array;

	const u32 num_tile_mode_states =

			ARRAY_SIZE(rdev->config.si.tile_mode_array);

	u32 reg_offset, split_equal_to_row_size;



	switch (rdev->config.si.mem_row_size_in_kb) {

	case 1:
@@ -2458,12 +2460,14 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
		break;

	}



	if ((rdev->family == CHIP_TAHITI) ||

	    (rdev->family == CHIP_PITCAIRN)) {

		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {

			switch (reg_offset) {

			case 0:  /* non-AA compressed depth or any compressed stencil */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

	for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

		tile[reg_offset] = 0;



	switch(rdev->family) {

	case CHIP_TAHITI:

	case CHIP_PITCAIRN:

		/* non-AA compressed depth or any compressed stencil */

		tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -2471,9 +2475,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 1:  /* 2xAA/4xAA compressed depth only */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* 2xAA/4xAA compressed depth only */

		tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
@@ -2481,9 +2484,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 2:  /* 8xAA compressed depth only */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* 8xAA compressed depth only */

		tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2491,9 +2493,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 3:  /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* 2xAA/4xAA compressed depth with stencil (for depth buffer) */

		tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
@@ -2501,9 +2502,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 4:  /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

		/* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */

		tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -2511,9 +2511,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 5:  /* Uncompressed 16bpp depth - and stencil buffer allocated with it */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* Uncompressed 16bpp depth - and stencil buffer allocated with it */

		tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(split_equal_to_row_size) |
@@ -2521,9 +2520,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 6:  /* Uncompressed 32bpp depth - and stencil buffer allocated with it */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* Uncompressed 32bpp depth - and stencil buffer allocated with it */

		tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(split_equal_to_row_size) |
@@ -2531,9 +2529,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));

				break;

			case 7:  /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* Uncompressed 8bpp stencil without depth (drivers typically do not use) */

		tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(split_equal_to_row_size) |
@@ -2541,9 +2538,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 8:  /* 1D and 1D Array Surfaces */

				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |

		/* 1D and 1D Array Surfaces */

		tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |

			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -2551,9 +2547,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 9:  /* Displayable maps. */

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

		/* Displayable maps. */

		tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -2561,9 +2556,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 10:  /* Display 8bpp. */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* Display 8bpp. */

		tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2571,9 +2565,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 11:  /* Display 16bpp. */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* Display 16bpp. */

		tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2581,9 +2574,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 12:  /* Display 32bpp. */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* Display 32bpp. */

		tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
@@ -2591,9 +2583,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));

				break;

			case 13:  /* Thin. */

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

		/* Thin. */

		tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -2601,9 +2592,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 14:  /* Thin 8 bpp. */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* Thin 8 bpp. */

		tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2611,9 +2601,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));

				break;

			case 15:  /* Thin 16 bpp. */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* Thin 16 bpp. */

		tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2621,9 +2610,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));

				break;

			case 16:  /* Thin 32 bpp. */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* Thin 32 bpp. */

		tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
@@ -2631,9 +2619,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));

				break;

			case 17:  /* Thin 64 bpp. */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* Thin 64 bpp. */

		tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(split_equal_to_row_size) |
@@ -2641,9 +2628,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));

				break;

			case 21:  /* 8 bpp PRT. */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* 8 bpp PRT. */

		tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2651,9 +2637,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 22:  /* 16 bpp PRT */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* 16 bpp PRT */

		tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2661,9 +2646,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));

				break;

			case 23:  /* 32 bpp PRT */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* 32 bpp PRT */

		tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2671,9 +2655,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 24:  /* 64 bpp PRT */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* 64 bpp PRT */

		tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
@@ -2681,9 +2664,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 25:  /* 128 bpp PRT */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* 128 bpp PRT */

		tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
@@ -2691,21 +2673,16 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));



		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

			WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);

		break;

			default:

				gb_tile_moden = 0;

				break;

			}

			rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;

			WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);

		}

	} else if ((rdev->family == CHIP_VERDE) ||

		   (rdev->family == CHIP_OLAND) ||

		   (rdev->family == CHIP_HAINAN)) {

		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {

			switch (reg_offset) {

			case 0:  /* non-AA compressed depth or any compressed stencil */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |



	case CHIP_VERDE:

	case CHIP_OLAND:

	case CHIP_HAINAN:

		/* non-AA compressed depth or any compressed stencil */

		tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -2713,9 +2690,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));

				break;

			case 1:  /* 2xAA/4xAA compressed depth only */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* 2xAA/4xAA compressed depth only */

		tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
@@ -2723,9 +2699,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));

				break;

			case 2:  /* 8xAA compressed depth only */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* 8xAA compressed depth only */

		tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2733,9 +2708,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));

				break;

			case 3:  /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* 2xAA/4xAA compressed depth with stencil (for depth buffer) */

		tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
@@ -2743,9 +2717,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));

				break;

			case 4:  /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

		/* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */

		tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -2753,9 +2726,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 5:  /* Uncompressed 16bpp depth - and stencil buffer allocated with it */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* Uncompressed 16bpp depth - and stencil buffer allocated with it */

		tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |

			   TILE_SPLIT(split_equal_to_row_size) |
@@ -2763,9 +2735,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 6:  /* Uncompressed 32bpp depth - and stencil buffer allocated with it */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* Uncompressed 32bpp depth - and stencil buffer allocated with it */

		tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |

			   TILE_SPLIT(split_equal_to_row_size) |
@@ -2773,9 +2744,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 7:  /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* Uncompressed 8bpp stencil without depth (drivers typically do not use) */

		tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |

			   TILE_SPLIT(split_equal_to_row_size) |
@@ -2783,9 +2753,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));

				break;

			case 8:  /* 1D and 1D Array Surfaces */

				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |

		/* 1D and 1D Array Surfaces */

		tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |

			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -2793,9 +2762,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 9:  /* Displayable maps. */

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

		/* Displayable maps. */

		tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -2803,9 +2771,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 10:  /* Display 8bpp. */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* Display 8bpp. */

		tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2813,9 +2780,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));

				break;

			case 11:  /* Display 16bpp. */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* Display 16bpp. */

		tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2823,9 +2789,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 12:  /* Display 32bpp. */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* Display 32bpp. */

		tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
@@ -2833,9 +2798,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 13:  /* Thin. */

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

		/* Thin. */

		tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -2843,9 +2807,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 14:  /* Thin 8 bpp. */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* Thin 8 bpp. */

		tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2853,9 +2816,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 15:  /* Thin 16 bpp. */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* Thin 16 bpp. */

		tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2863,9 +2825,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 16:  /* Thin 32 bpp. */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* Thin 32 bpp. */

		tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
@@ -2873,9 +2834,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 17:  /* Thin 64 bpp. */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* Thin 64 bpp. */

		tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |

			   TILE_SPLIT(split_equal_to_row_size) |
@@ -2883,9 +2843,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 21:  /* 8 bpp PRT. */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* 8 bpp PRT. */

		tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2893,9 +2852,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 22:  /* 16 bpp PRT */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* 16 bpp PRT */

		tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2903,9 +2861,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));

				break;

			case 23:  /* 32 bpp PRT */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* 32 bpp PRT */

		tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2913,9 +2870,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 24:  /* 64 bpp PRT */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* 64 bpp PRT */

		tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
@@ -2923,9 +2879,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));

				break;

			case 25:  /* 128 bpp PRT */

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

		/* 128 bpp PRT */

		tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
@@ -2933,17 +2888,15 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) 
			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));



		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

			WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);

		break;



	default:

				gb_tile_moden = 0;

				break;

			}

			rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;

			WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);

		}

	} else

		DRM_ERROR("unknown asic: 0x%x\n", rdev->family);

	}

}



static void si_select_se_sh(struct radeon_device *rdev,

			    u32 se_num, u32 sh_num)