Commit 1037b82f authored by Dave Jiang's avatar Dave Jiang Committed by Dan Williams
Browse files

cxl: Store the access coordinates for the generic ports 



Each CXL host bridge is represented by an ACPI0016 device. A generic port
device handle that is an ACPI device is represented by a string of
ACPI0016 device HID and UID. Create a device handle from the ACPI device
and retrieve the access coordinates from the stored memory targets. The
access coordinates are stored under the cxl_dport that is associated with
the CXL host bridge.

The access coordinates struct is dynamically allocated under cxl_dport in
order for code later on to detect whether the data exists or not.

Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/170319623196.2212653.17916695743464172534.stgit@djiang5-mobl3


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent f2202f99

drivers/cxl/acpi.c

+25 −0
Original line number Diff line number Diff line
@@ -513,8 +513,29 @@ static int cxl_get_chbs(struct device *dev, struct acpi_device *hb, 
	return 0;

}



static int get_genport_coordinates(struct device *dev, struct cxl_dport *dport)

{

	struct acpi_device *hb = to_cxl_host_bridge(NULL, dev);

	u32 uid;

	int rc;



	if (kstrtou32(acpi_device_uid(hb), 0, &uid))

		return -EINVAL;



	rc = acpi_get_genport_coordinates(uid, &dport->hb_coord);

	if (rc < 0)

		return rc;



	/* Adjust back to picoseconds from nanoseconds */

	dport->hb_coord.read_latency *= 1000;

	dport->hb_coord.write_latency *= 1000;



	return 0;

}



static int add_host_bridge_dport(struct device *match, void *arg)

{

	int ret;

	acpi_status rc;

	struct device *bridge;

	struct cxl_dport *dport;
@@ -564,6 +585,10 @@ static int add_host_bridge_dport(struct device *match, void *arg) 
	if (IS_ERR(dport))

		return PTR_ERR(dport);



	ret = get_genport_coordinates(match, dport);

	if (ret)

		dev_dbg(match, "Failed to get generic port perf coordinates.\n");



	return 0;

}

drivers/cxl/cxl.h

+2 −0
Original line number Diff line number Diff line
@@ -661,6 +661,7 @@ struct cxl_rcrb_info { 
 * @port: reference to cxl_port that contains this downstream port

 * @regs: Dport parsed register blocks

 * @sw_coord: access coordinates (performance) for switch from CDAT

 * @hb_coord: access coordinates (performance) from ACPI generic port (host bridge)

 * @link_latency: calculated PCIe downstream latency

 */

struct cxl_dport {
@@ -672,6 +673,7 @@ struct cxl_dport { 
	struct cxl_port *port;

	struct cxl_regs regs;

	struct access_coordinate sw_coord;

	struct access_coordinate hb_coord;

	long link_latency;

};