Commit 1099b651 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-fixes-2026-02-05' of... 

Merge tag 'drm-intel-next-fixes-2026-02-05' of https://gitlab.freedesktop.org/drm/i915/kernel

 into drm-next

- Fix the pixel normalization handling for xe3p_lpd display

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patch.msgid.link/aYROngKfyUIyoQW0@jlahtine-mobl
parents 3cc9398a 3e28a67a

drivers/gpu/drm/i915/display/intel_display_device.h

+1 −0
Original line number Diff line number Diff line
@@ -193,6 +193,7 @@ struct intel_display_platforms { 
#define HAS_MSO(__display)		(DISPLAY_VER(__display) >= 12)

#define HAS_OVERLAY(__display)		(DISPLAY_INFO(__display)->has_overlay)

#define HAS_PIPEDMC(__display)		(DISPLAY_VER(__display) >= 12)

#define HAS_PIXEL_NORMALIZER(__display)	(DISPLAY_VER(__display) >= 35)

#define HAS_PSR(__display)		(DISPLAY_INFO(__display)->has_psr)

#define HAS_PSR_HW_TRACKING(__display)	(DISPLAY_INFO(__display)->has_psr_hw_tracking)

#define HAS_PSR2_SEL_FETCH(__display)	(DISPLAY_VER(__display) >= 12)

drivers/gpu/drm/i915/display/intel_fbc.c

+6 −4
Original line number Diff line number Diff line
@@ -1215,13 +1215,15 @@ static bool xe3p_lpd_fbc_pixel_format_is_valid(const struct intel_plane_state *p 
	}

}



bool

intel_fbc_is_enable_pixel_normalizer(const struct intel_plane_state *plane_state)

bool intel_fbc_need_pixel_normalizer(const struct intel_plane_state *plane_state)

{

	struct intel_display *display = to_intel_display(plane_state);



	return DISPLAY_VER(display) >= 35 &&

	       xe3p_lpd_fbc_fp16_format_is_valid(plane_state);

	if (HAS_PIXEL_NORMALIZER(display) &&

	    xe3p_lpd_fbc_fp16_format_is_valid(plane_state))

		return true;



	return false;

}



static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)

drivers/gpu/drm/i915/display/intel_fbc.h

+1 −2
Original line number Diff line number Diff line
@@ -56,7 +56,6 @@ void intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state, 
				  struct intel_crtc *crtc);

void intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,

				       struct intel_plane *plane);

bool

intel_fbc_is_enable_pixel_normalizer(const struct intel_plane_state *plane_state);

bool intel_fbc_need_pixel_normalizer(const struct intel_plane_state *plane_state);



#endif /* __INTEL_FBC_H__ */

drivers/gpu/drm/i915/display/skl_universal_plane.c

+18 −18
Original line number Diff line number Diff line
@@ -891,23 +891,20 @@ static void icl_plane_disable_sel_fetch_arm(struct intel_dsb *dsb, 
	intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0);

}



static void x3p_lpd_plane_update_pixel_normalizer(struct intel_dsb *dsb,

						  struct intel_plane *plane,

						  bool enable)

static bool plane_has_normalizer(struct intel_plane *plane)

{

	struct intel_display *display = to_intel_display(plane);

	enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(plane->pipe);

	u32 val;



	/* Only HDR planes have pixel normalizer and don't matter if no FBC */

	if (!skl_plane_has_fbc(display, fbc_id, plane->id))

		return;

	return HAS_PIXEL_NORMALIZER(display) && icl_is_hdr_plane(display, plane->id);

}



	val = enable ? PLANE_PIXEL_NORMALIZE_NORM_FACTOR(PLANE_PIXEL_NORMALIZE_NORM_FACTOR_1_0) |

		       PLANE_PIXEL_NORMALIZE_ENABLE : 0;

static u32 pixel_normalizer_value(const struct intel_plane_state *plane_state)

{

	if (!intel_fbc_need_pixel_normalizer(plane_state))

		return 0;



	intel_de_write_dsb(display, dsb,

			   PLANE_PIXEL_NORMALIZE(plane->pipe, plane->id), val);

	return PLANE_PIXEL_NORMALIZE_ENABLE |

	       PLANE_PIXEL_NORMALIZE_NORM_FACTOR(PLANE_PIXEL_NORMALIZE_NORM_FACTOR_1_0);

}



static void
@@ -926,8 +923,9 @@ icl_plane_disable_arm(struct intel_dsb *dsb, 


	icl_plane_disable_sel_fetch_arm(dsb, plane, crtc_state);



	if (DISPLAY_VER(display) >= 35)

		x3p_lpd_plane_update_pixel_normalizer(dsb, plane, false);

	if (plane_has_normalizer(plane))

		intel_de_write_dsb(display, dsb,

				   PLANE_PIXEL_NORMALIZE(plane->pipe, plane->id), 0);



	intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0);

	intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 0);
@@ -1676,11 +1674,13 @@ icl_plane_update_arm(struct intel_dsb *dsb, 


	/*

	 * In order to have FBC for fp16 formats pixel normalizer block must be

	 * active. Check if pixel normalizer block need to be enabled for FBC.

	 * If needed, use normalization factor as 1.0 and enable the block.

	 * active. For FP16 formats, use normalization factor as 1.0 and enable

	 * the block.

	 */

	if (intel_fbc_is_enable_pixel_normalizer(plane_state))

		x3p_lpd_plane_update_pixel_normalizer(dsb, plane, true);

	if (plane_has_normalizer(plane))

		intel_de_write_dsb(display, dsb,

				   PLANE_PIXEL_NORMALIZE(plane->pipe, plane->id),

				   pixel_normalizer_value(plane_state));



	/*

	 * The control register self-arms if the plane was previously