Commit 10a3dabd authored by Thiemo Seufer's avatar Thiemo Seufer Committed by Ralf Baechle
Browse files

Add/Fix missing bit of R4600 hit cacheop workaround. 



Signed-off-by: default avatarThiemo Seufer <ths@networkno.de>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 02fe2c9c

arch/mips/mm/c-r4k.c

+1 −0
Original line number Diff line number Diff line
@@ -481,6 +481,7 @@ static inline void local_r4k_flush_icache_range(void *args) 
		if (end - start > dcache_size) {

			r4k_blast_dcache();

		} else {

			R4600_HIT_CACHEOP_WAR_IMPL;

			addr = start & ~(dc_lsize - 1);

			aend = (end - 1) & ~(dc_lsize - 1);

arch/mips/mm/pg-r4k.c

+1 −1
Original line number Diff line number Diff line
@@ -209,7 +209,7 @@ static inline void build_cdex_p(void) 
	}



	if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())

		build_insn_word(0x8c200000);	/* lw      $zero, ($at) */

		build_insn_word(0x3c01a000);	/* lui     $at, 0xa000  */



	mi.c_format.opcode     = cache_op;

	mi.c_format.rs         = 4;		/* $a0 */