Commit 10a9c09a authored by Asad Kamal's avatar Asad Kamal Committed by Alex Deucher
Browse files

drm/amd/pm: Allow to set power cap in vf mode 



Allow setting power cap for smu_v13_0_6 in 1vf mode

Signed-off-by: default avatarAsad Kamal <asad.kamal@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 780f7a45

drivers/gpu/drm/amd/pm/amdgpu_pm.c

+4 −3
Original line number Diff line number Diff line
@@ -3254,9 +3254,6 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, 
	int err;

	u32 value;



	if (amdgpu_sriov_vf(adev))

		return -EINVAL;



	err = kstrtou32(buf, 10, &value);

	if (err)

		return err;
@@ -3598,6 +3595,10 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, 
			return 0;

	}



	if (attr == &sensor_dev_attr_power1_cap.dev_attr.attr &&

	    amdgpu_virt_cap_is_rw(&adev->virt.virt_caps, AMDGPU_VIRT_CAP_POWER_LIMIT))

		effective_mode |= S_IWUSR;



	/* not implemented yet for APUs having < GC 9.3.0 (Renoir) */

	if (((adev->family == AMDGPU_FAMILY_SI) ||

	     ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) &&

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

+5 −1
Original line number Diff line number Diff line
@@ -143,7 +143,7 @@ static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COU 
	MSG_MAP(GetMinDpmFreq,			     PPSMC_MSG_GetMinDpmFreq,			1),

	MSG_MAP(GetMaxDpmFreq,			     PPSMC_MSG_GetMaxDpmFreq,			1),

	MSG_MAP(GetDpmFreqByIndex,		     PPSMC_MSG_GetDpmFreqByIndex,		1),

	MSG_MAP(SetPptLimit,			     PPSMC_MSG_SetPptLimit,			0),

	MSG_MAP(SetPptLimit,			     PPSMC_MSG_SetPptLimit,			1),

	MSG_MAP(GetPptLimit,			     PPSMC_MSG_GetPptLimit,			1),

	MSG_MAP(GfxDeviceDriverReset,		     PPSMC_MSG_GfxDriverReset,			SMU_MSG_RAS_PRI | SMU_MSG_NO_PRECHECK),

	MSG_MAP(DramLogSetDramAddrHigh,		     PPSMC_MSG_DramLogSetDramAddrHigh,		0),
@@ -413,6 +413,10 @@ static void smu_v13_0_6_init_caps(struct smu_context *smu) 
			smu_v13_0_6_cap_set(smu, SMU_CAP(HST_LIMIT_METRICS));



		if (amdgpu_sriov_vf(adev)) {

			if (fw_ver >= 0x00558200)

				amdgpu_virt_attr_set(&adev->virt.virt_caps,

						     AMDGPU_VIRT_CAP_POWER_LIMIT,

						     AMDGPU_CAP_ATTR_RW);

			if ((pgm == 0 && fw_ver >= 0x00558000) ||

			    (pgm == 7 && fw_ver >= 0x7551000)) {

				smu_v13_0_6_cap_set(smu,